LTC1709EG-7 Linear Technology, LTC1709EG-7 Datasheet - Page 22

• Manufacturer Part Number: LTC1709EG-7
• Description: IC SW REG STEP-DOWN SYNC 36-SSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC1709EG-7

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 1.3 ~ 3.5 V
• Current - Output: 3A
• Voltage - Input: 4 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Frequency - Switching: -

APPLICATIO S I FOR ATIO
LTC1709-7
synchronous MOSFET. If the two MOSFETs have approxi-
mately the same R
MOSFET can simply be summed with the resistances of L,
R
R
total resistance is 25m . This results in losses ranging
from 2% to 8% as the output current increases from 3A to
15A per output stage for a 5V output, or a 3% to 12% loss
per output stage for a 3.3V output. Efficiency varies as the
inverse square of V
and output power level. The combined effects of increas-
ingly lower output voltages and higher currents required
by high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!
2) Transition losses apply only to the topside MOSFET(s),
and are significant only when operating at high input
voltages (typically 12V or greater). Transition losses can
be estimated from:
3) INTV
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTV
ground. The resulting dQ/dt is a current out of INTV
is typically much larger than the control circuit current. In
continuous mode, I
are the gate charges of the topside and bottom side
MOSFETs.
Supplying INTV
from an output-derived source will scale the V
required for the driver and control circuits by the ratio
(Duty Factor)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTV
mately 3mA of V
loss from 10% or more (if the driver was powered directly
from V
4) The V
DC supply current given in the Electrical Characteristics
table, which excludes MOSFET driver and control cur-
rents; the second is the current drawn from the differential
22
SENSE
DS(ON)
Transition Loss = (1.7) V
IN
and ESR to obtain I
CC
= 10m , R
) to only a few percent.
IN
current is the sum of the MOSFET driver and
current has two components: the first is the
CC
IN
power through the EXTV
L
OUT
current. This reduces the mid-current
U
GATECHG
= 10m , and R
DS(ON)
for the same external components
U
2
, then the resistance of one
CC
IN
R losses. For example, if each
= (Q
2
current results in approxi-
I
O(MAX)
T
+ Q
SENSE
W
B
), where Q
C
RSS
= 5m , then the
CC
f
switch input
U
IN
T
current
and Q
CC
CC
that
to
B
amplifier output. V
(<0.1%) loss.
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses in the
design of a system. The internal battery and input fuse
resistance losses can be minimized by making sure that
C
the switching frequency. A 50W supply will typically
require a minimum of 200 F to 300 F of output capaci-
tance having a maximum of 10m to 20m of ESR. The
LTC1709-7 2-phase architecture typically halves the
input and output capacitance requirements over compet-
ing solutions. Other losses including Schottky conduc-
tion losses during dead-time and inductor core losses
generally account for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V
amount equal to I
series resistance of C
discharge C
forces the regulator to adapt to the current change and
return V
time V
ringing, which would indicate a stability problem. The
availability of the I
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time, and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin. The I
shown in the Figure 1 circuit will provide an adequate
starting point for most applications.
The I
loop compensation. The values can be modified slightly
IN
has adequate charge storage and a very low ESR at
TH
OUT
OUT
series R
can be monitored for excessive overshoot or
OUT
to its steady-state value. During this recovery
generating the feedback error signal that
C
-C
TH
IN
LOAD
C
OUT
pin not only allows optimization of
current typically results in a small
filter sets the dominant pole-zero
(ESR), where ESR is the effective
( I
LOAD
TH
) also begins to charge or
external components
OUT
shifts by an