LT1725CGN#PBF Linear Technology, LT1725CGN#PBF Datasheet - Page 20

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LT1725CGN#PBF

Manufacturer Part Number
LT1725CGN#PBF
Description
IC CTRLR ISO FLYBACK HV 16SSOP
Manufacturer
Linear Technology
Type
Flybackr
Datasheet

Specifications of LT1725CGN#PBF

Internal Switch(s)
No
Synchronous Rectifier
No
Number Of Outputs
1
Frequency - Switching
50kHz ~ 250kHz
Operating Temperature
0°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
16-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output
-
Voltage - Output
-
Voltage - Input
-
Power - Output
-

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APPLICATIO S I FOR ATIO
LT1725
MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS
The LT1725 is a current mode controller. It uses the V
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the V
node, nominally 2.5V, then acts as an output switch peak
current limit.
This 2.5V at the V
at the I
than 40%. For a duty cycle above 40%, the internal slope
compensation mechanism lowers the effective I
voltage limit. For example, at a duty cycle of 80%, the
nominal I
comes the switch current limit specification. Maximum
available output power is then determined by the switch
current limit, which is somewhat duty cycle dependent
due to internal slope compensation action.
Overcurrent conditions are handled by the same mecha-
nism. The output switch turns on, the peak current is
quickly reached and the switch is turned off. Because the
output switch is only on for a small fraction of the available
period, power dissipation is controlled.
Loss of current limit is possible under certain conditions.
Remember that the LT1725 normally exhibits a minimum
switch on time, irrespective of current trip point. If the duty
cycle exhibited by this minimum on time is greater than the
ratio of secondary winding voltage (referred-to-primary)
divided by input voltage, then peak current will not be
controlled at the nominal value, and will cycle-by-cycle
ratchet up to some higher level. Expressed mathemati-
cally, the requirement to maintain short-circuit control is:
20
t
I
V
R
t
f = switching frequency
ON
SC
ON
F
SEC
= output diode forward voltage at I
= short-circuit output current
= output switch minimum on time
SENSE
= resistance of transformer secondary
f
SENSE
<
(
pin, when the (ON) switch duty cycle is less
V
F
+
V
voltage limit is 220mV. This action be-
IN
C
I
SC
U
pin corresponds to a value of 250mV
N
SP
R
SEC
U
)
where
W
SC
U
SENSE
C
C
Trouble is typically only encountered in applications with
a relatively high product of input voltage times secondary-
to-primary turns ratio and/or a relatively long minimum
switch on time. (Additionally, several real world effects such
as transformer leakage inductance, AC winding losses, and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate.)
THERMAL CONSIDERATIONS
Care should be taken to ensure that the worst-case input
voltage condition does not cause excessive die tempera-
tures. The 16-lead SO package is rated at 100°C/W, and
the 16-lead GN at 110°C/W.
Average supply current is simply the sum of quiescent
current given in the specifications section plus gate drive
current. Gate drive current can be computed as:
(Note: Total gate charge is more complicated than C
as it is frequently dominated by Miller effect of the C
Furthermore, both capacitances are nonlinear in practice.
Fortunately, most MOSFET data sheets provide figures
and graphs which yield the total gate charge directly per
operating conditions.) Nearly all gate drive power is dissi-
pated in the IC, except for a small amount in the external
gate series resistor, so total IC dissipation may be com-
puted as:
V
N
I
Q
f = switching frequency
P
I
Q
f = switching frequency
V
G
Q
IN
D(TOTAL)
CC
SP
G
G
= f • Q
= quiescent current (from specifications)
= total gate charge
= total gate charge
= input voltage
= LT1725 supply voltage
= secondary-to-primary turns ratio ( N
G
= V
where
CC
(I
Q
+ • f • Q
G
), where
SEC
/N
GS
PRI
1725fa
• V
GD
)
G
.

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