LT1576IS8-5 Linear Technology, LT1576IS8-5 Datasheet - Page 21

• Manufacturer Part Number: LT1576IS8-5
• Description: IC REG SW 5V 1.5A STEPDOWN 8SOIC
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LT1576IS8-5

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 5V
• Current - Output: 1.5A
• Frequency - Switching: 200kHz
• Voltage - Input: 5 ~ 25 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIONS
Analog experts will note that around 7kHz, phase dips
close to the zero phase margin line. This is typical of
switching regulators, especially those that operate over a
wide range of loads. This region of low phase is not a
problem as long as it does not occur near unity-gain. In
practice, the variability of output capacitor ESR tends to
dominate all other effects with respect to loop response.
Variations in ESR will cause unity-gain to move around,
but at the same time phase moves with it so that adequate
phase margin is maintained over a very wide range of ESR
(
What About a Resistor in the Compensation Network?
It is common practice in switching regulator design to add
a “zero” to the error amplifier compensation to increase
loop phase margin. This zero is created in the external
network in the form of a resistor (R
compensation capacitor. Increasing the size of this resis-
tor generally creates better and better loop stability, but
there are two limitations on its value. First, the combina-
tion of output capacitor ESR and a large value for R
cause loop gain to stop rolling off altogether, creating a
gain margin problem. An approximate formula for R
where gain margin falls to zero is:
G
G
ESR = Output capacitor ESR
1.21 = Reference voltage
With V
would yield zero gain margin, so this represents an upper
limit. There is a second limitation however which has
nothing to do with theoretical small signal dynamics. This
resistor sets high frequency gain of the error amplifier,
including the gain at the switching frequency. If switching
frequency gain is high enough, output ripple voltage will
appear at the V
proper operation of the regulator. In the marginal case,
MP
MA
R Loop
3:1).
C
= Transconductance of power stage = 1.5A/V
= Error amplifier transconductance = 1(10
OUT
= 5V and ESR = 0.1 , a value of 27.5k for R
Gain = 1
C
pin with enough amplitude to muck up
U
INFORMATION
G
U
MP
G
MA
V
W
OUT
C
) in series with the
ESR
1 21
U
–3
)
C
may
C
C
subharmonic switching occurs, as evidenced by alternat-
ing pulse widths seen at the switch node. In more severe
cases, the regulator squeals or hisses audibly even though
the output voltage is still roughly correct. None of this will
show on a theoretical Bode plot because Bode is an
amplitude insensitive analysis. Tests have shown that if
ripple voltage on the V
LT1576 will be well behaved. The formula below will give
an estimate of V
loop, assuming that R
of C
G
If a computer simulation of the LT1576 showed that a
series compensation resistor of 15k gave best overall loop
response, with adequate gain margin, the resulting V
ripple voltage with V
L = 30 H, would be:
This ripple voltage is high enough to possibly create
subharmonic switching. In most situations a compromise
value (< 10k in this case) for the resistor gives acceptable
phase margin and no subharmonic problems. In other
cases, the resistor may have to be larger to get acceptable
phase response, and some means must be used to control
ripple voltage at the V
is to add a capacitor (C
on the V
set at one-fifth of switching frequency so that it provides
significant attenuation of switching ripple, but does not
add unacceptable phase shift at loop unity-gain frequency.
With R
MA
V
V
C
C
C RIPPLE
C RIPPLE
F
= Error amplifier transconductance (1000 Mho)
at 200kHz.
C
C
= 15k,
2
pin. Pole frequency for this capacitor is typically
5
f R
15
C
R
C
ripple voltage when R
k
C
10 30 10
IN
1 10
C
C
C
G
F
2 200 10
•
) in parallel with the R
pin. The suggested way to do this
is large compared to the reactance
is held to less than 100mV
MA
= 10V, V
•
3
LT1576/LT1576-5
V
IN
10 5 0 1 1 21
V
•
6
5
IN
OUT
3
200 10
V
L f
OUT
15
= 5V, ESR = 0.1 ,
•
.
k
C
ESR
3
is added to the
.
C
265
/C
1 21
C
pF
network
21
0 151
P-P
.
C
, the
pin
V