LTC1735CGN#TR Linear Technology, LTC1735CGN#TR Datasheet - Page 26

• Manufacturer Part Number: LTC1735CGN#TR
• Description: IC REG SW SYNC STEPDWN HE 16SSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC1735CGN#TR

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.8 ~ 6 V
• Current - Output: 3A
• Frequency - Switching: 300kHz
• Voltage - Input: 4 ~ 30 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIO S I FOR ATIO
LTC1735
Next verify the minimum on-time of 200ns is not violated.
The minimum on-time occurs at maximum V
Since the output voltage is below 2.4V the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the sense pin current.
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Siliconix Si4412ADY results
in R
voltage with T(estimated) = 50 C:
Because the duty cycle of the bottom MOSFET is much
greater than the top, a larger MOSFET, Siliconix Si4410DY,
(R
bottom MOSFET, again assuming T
Thanks to current foldback, the bottom MOSFET dissipa-
tion in short-circuit will be less than under full load
conditions.
26
P
MAIN
DS(ON)
R
P
t
ON MIN
DS(ON)
SYNC
1
(
MAX
(
204
1 8
1 7 22
= 0.02 ) is chosen. The power dissipation in the
22
)
.
.
)
= 0.035 , C
505
22
V
V
mW
24
24
V
V
5 1 0 005 50
22
mW
IN MAX
V
k
k
V
– .
2
(
OUT
2
V
1 8
2 4
2 4
U
.
.
5
A
V
V V
V
)
0 8
0 8
( .
f
RSS
.
.
–
– .
5
100
U
V
V
1 8
A
22 300
OUT
= 100pF. At maximum input
2
pF
)(
V
V
1 1 0 02
(
1 8
.
.
300
V
C
W
32
A
kHz
.
–
= 50 C, is:
kHz
k
25
)
C
273
)
IN
0 035
U
:
.
ns
C
temperature. C
output ripple. The output ripple in continuous mode will be
highest at the maximum input voltage. The worst-case
output voltage ripple due to ESR is approximately:
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1735. These items are also illustrated graphically in
the layout diagram of Figure 12. Check the following in
your layout:
1) Are the signal and power grounds segregated? The
LTC1735 PGND pin should tie to the ground plane close to
the input capacitor(s). The SGND pin should then connect
to PGND, and all components that connect to SGND
should make a single point tie to the SGND pin. The
synchronous MOSFET source pins should connect to the
input capacitor(s) ground.
2) Does the V
resistors? The resistive divider R1, R2 must be connected
between the (+) plate of C
to 100pF capacitor should be as close as possible to the
LTC1735. Be careful locating the feedback resistors too far
away from the LTC1735. The V
routed close to any other nodes with high slew rates.
3) Are the SENSE
minimum PC trace spacing? The filter capacitor between
SENSE
LTC1735. Ensure accurate current sensing with Kelvin
connections as shown in Figure 13. Series resistance can
be added to the SENSE lines to increase noise rejection.
4) Does the (+) terminal of C
topside MOSFET(s) as closely as possible? This capacitor
provides the AC current to the MOSFET(s).
5) Is the INTV
between INTV
tor carries the MOSFET driver peak currents. An addi-
tional 1 F ceramic capacitor placed immediately next to
IN
V
is chosen for an RMS current rating of at least 2.5A at
ORIPPLE
+
and SENSE
OSENSE
CC
CC
OUT
R
decoupling capacitor connected closely
ESR
and the power ground pin? This capaci-
–
and SENSE
is chosen with an ESR of 0.02 for low
–
(
pin connect directly to the feedback
should be as close as possible to the
I
L
OUT
)
IN
0 02 2 3
and signal ground. The 47pF
+
.
connect to the drain of the
OSENSE
leads routed together with
( .
line should not be
A
)
46
mV
P P
1735fc