LTC1149CS-5#TRPBF Linear Technology, LTC1149CS-5#TRPBF Datasheet - Page 6

• Manufacturer Part Number: LTC1149CS-5#TRPBF
• Description: IC SW REG STEP-DOWN 5V 16-SOIC
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC1149CS-5#TRPBF

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 5V
• Current - Output: 50mA
• Frequency - Switching: 250kHz
• Voltage - Input: 0 ~ 48 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

OPERATIO
FU CTIO AL DIAGRA
LTC1149
LTC1149-3.3/LTC1149-5
current is made proportional to the output voltage (mea-
sured by Pin 8) to model the inductor current, which
decays at a rate which is also proportional to the output
voltage. While the timing capacitor is discharging, the
NGATE output is high, turning on the N-channel MOSFET.
When the voltage on the timing capacitor has discharged
past V
causes the NGATE output to go low (turning off the
N-channel MOSFET) and the PGATE output to also go low
(turning the P-channel MOSFET back on). The cycle then
repeats.
As the load current increases, the output voltage
decreases slightly. This causes the output of the gain
stage to increase the current comparator threshold, thus
tracking the load current.
The sequence of events for Burst Mode operation is very
similar to continuous operation with the cycle interrupted
by the voltage comparator. When the output voltage is at
or above the desired regulated value, the P-channel MOSFET
is held off by comparator V and the timing capacitor
continues to discharge below V
capacitor discharges past V
trips, causing the internal SLEEP line to go low and the
N-channel MOSFET to turn off.
6
U
TH1
, comparator T trips, setting the flip-flop. This
SHDN2
V
15
2
IN
U
SLEEP
S
U
+
–
REGULATOR
DROPOUT
(Refer to Functional Diagram)
V TH2
LOW
10V
14 RGND
C
6
TH2
T
, voltage comparator S
CAP
V
16
CC
3
TH1
V
TH1
W
. When the timing
500k
–
CONTROL
Q
+
OFF-TIME
Pin 10 connection shown for LTC1149-3.3 and LTC1149-5; changes create LTC1149.
T
R
S
V
SENSE
IN
–
The circuit now enters sleep mode with both power
MOSFETs turned off. In sleep mode, much of the circuitry
is turned off, dropping the supply current from several
milliamperes (with the MOSFETs switching) to 600 A.
When the output capacitor has discharged by the amount
of hysteresis in comparator V, the P-channel MOSFET is
again turned on and this process repeats. To avoid the
operation of the current loop interfering with Burst Mode
operation, a built-in offset is incorporated in the gain
stage. This prevents the current comparator threshold
from increasing until the output voltage has dropped
below a minimum threshold.
To prevent both the external MOSFETs from ever being
turned on at the same time, feedback is incorporated to
sense the state of the driver output pins. Before the N-gate
output can go high, the P-drive output must also be high.
Likewise, the P-drive output is prevented from going low
when the N-gate output is high.
Using constant off-time architecture, the operating fre-
quency is a function of the input voltage. To minimize the
frequency variation as dropout is approached, the off-
time controller increases the discharge current as V
drops below V
MOSFET is turned on continuously.
C
–
+
I
TH
7
13k
V
25mV TO 150mV
–
+
SGND
11
12 PGND
G
OUT
5 V
–
+
REFERENCE
CC
+ 1.5V. In dropout the P-channel
500k
1.25V
13
1
4
9 SENSE
PGATE
PDRIVE
NGATE
V
OS
+
SHDN1
(V
10
FB
)
8 SENSE
100k
1149 FD
–
IN