LTC3728LEUH#TR Linear Technology, LTC3728LEUH#TR Datasheet - Page 25

• Manufacturer Part Number: LTC3728LEUH#TR
• Description: IC REG SW DUAL 2PH STPDWN 32QFN
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck)r

Specifications of LTC3728LEUH#TR

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.8 ~ 7 V
• Current - Output: 3A
• Frequency - Switching: 250kHz ~ 550kHz
• Voltage - Input: 4.5 ~ 28 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIONS INFORMATION
If V
temporary continuous switching operation until V
again above its minimum.
In order to prevent erratic operation if no external connec-
tions are made to the FCB pin, the FCB pin has a 0.18μA
internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.
The following table summarizes the possible states avail-
able on the FCB pin:
Table 1
FCB Pin
0V to 0.75V
0.85V < V
Feedback Resistors
>4.8V
Voltage Positioning
Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifi cations. Voltage positioning can easily be added
to either or both controllers by loading the I
a resistive divider having a Thevenin equivalent voltage
source equal to the midpoint operating voltage range of
the error amplifi er, or 1.2V (see Figure 8).
SEC
FCB
drops below this level, the FCB voltage forces
< 4.3V
Figure 8. Active Voltage Positioning
Applied to the LTC3728L/LTC3728LX
INTV
CC
R
R
T2
T1
Condition
Forced Continuous Both Controllers
(Current Reversal Allowed— Burst Inhibited)
Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed
Regulating a Secondary Winding
Burst Mode Operation Disabled
Constant-Frequency Mode Enabled
No Current Reversal Allowed
No Minimum Peak Current
R
C
C
C
I
TH
LTC3728LX
LTC3728L/
3728 F08
TH
pin with
SEC
is
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifi er. The
maximum output voltage deviation can theoretically be
reduced to half, or alternatively the amount of output
capacitance can be reduced for a particular application.
A complete explanation is included in Design Solutions
10 (see www.linear.com).
Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Percent effi ciency can
be expressed as:
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3728L/LTC3728LX circuits: 1) IC V
current (including loading on the 3.3V internal regulator),
2) INTV
MOSFET transition losses.
1. The V
2. INTV
DC supply current given in the Electrical Characteristics
table, which excludes MOSFET driver and control cur-
rents; the second is the current drawn from the 3.3V
linear regulator output. V
a small (<0.1%) loss.
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high
to low again, a packet of charge dQ moves from INTV
to ground. The resulting dQ/dt is a current out of INTV
that is typically much larger than the control circuit
current. In continuous mode, I
where Q
and bottom side MOSFETs.
%Effi ciency = 100% – (L1 + L2 + L3 + ...)
CC
CC
IN
current is the sum of the MOSFET driver and
current has two components: the fi rst is the
T
regulator current, 3) I
and Q
LTC3728L/LTC3728LX
B
are the gate charges of the topside
IN
current typically results in
2
GATECHG
R losses, 4) Topside
= f(Q
T
25
+ Q
3728lxfe
B
CC
CC
IN
),