S-8335A120FT-TB-G Seiko Instruments, S-8335A120FT-TB-G Datasheet - Page 28

• Manufacturer Part Number: S-8335A120FT-TB-G
• Description: IC REG SW 3CH STEP UP 24-TSSOP
• Manufacturer: Seiko Instruments
• Type: Step-Up (Boost), Invertingr

Specifications of S-8335A120FT-TB-G

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 6.66 ~ 12.41 V, -4.61 ~ -8.59 V
• Frequency - Switching: 100kHz
• Voltage - Input: 2.4 ~ 5 V
• Operating Temperature: -20°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Power - Output: 650mW
• Output Voltage: 12.41 V
• Operating Temperature Range: - 20 C to + 70 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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STEP-UP, FOR LCD BIAS SUPPLY, 3-CHANNEL SWITCHING REGULATOR
S-8335 Series
Pattern Diagram
In general, the switching regulator is significantly affected by the circuit board wiring. The following figure
shows a sample pattern diagram for which the effect of the circuit board wiring is small.
Note the following points when creating a pattern diagram.
• There are two VSS lines (connected inside the IC).
• Arrange the VSS line and capacitors first. CVBAT, CL1, CL2, and CL3 are particularly important. Draw
• Basically, make the GND part of the circuit board as broad as possible and keep the impedance low.
• There are two VBAT lines (not connected inside the IC).
• Connect CL3 at both pin No. 19 (VDDX) and pin No. 21 (VOUT3) if possible (for example, connect
• Do not use through holes at locations for connecting CL1 to CL3.
• Increasing CL1 makes the output more stable. If the DC/DC P output fluctuates due to ripple, and this
a) VSS (pin No. 5): Large current GND
b) VSS (pin No. 17): Small current (analog) + middle current GND
the VSS line as wide as possible.
a) VBAT (pin No. 12): Reference (low noise)
b) VBAT (pin No. 16): All others (semi-low noise)
6.8 µF at each pin).
causes VQERR to frequently exceed the DC/DC Q error amplifier threshold value, then DC/DC Q
oscillates more than necessary and the DC/DC Q efficiency will decrease. Therefore, stabilizing the
DC/DC P output will also improve DC/DC Q efficiency.
Figure 20 Pattern Diagram
Seiko Instruments Inc.
59 mm
55 mm
Rev.6.0
_01