SC121ULTRT Semtech, SC121ULTRT Datasheet - Page 18

• Manufacturer Part Number: SC121ULTRT
• Description: IC BOOST SYNC 1.2A MLPD-6
• Manufacturer: Semtech
• Type: Step-Up (Boost)r

Specifications of SC121ULTRT

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 3.3V, 1.8 ~ 5 V
• Current - Output: 1.2A
• Frequency - Switching: 1.2MHz
• Voltage - Input: 0.7 ~ 4.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 6-MLPD-UT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Other names: SC121ULTRTTR

Applications Information (continued)
duty cycle must remain between 20% and 90% for the
device to operate within specifi cation.
Note that startup with a regulated active load is not the
same as startup with a resistive load. The resistive load
output current increases proportionately as the output
voltage rises until it reaches programmed V
a regulated active load presents a constant load as the
output voltage rises from 0V to programmed V
also that if the load applied to the output exceeds an
applicable V
cycle limit, the criterion to advance to the next startup
stage may not be achieved. In this situation startup may
pause at a reduced output voltage until the load is reduced
further.
Output Overload and Recovery
The PWM steady state duty cycle is determined by
D = 1 – (V
tice to overcome dissipative losses. As the output load
increases, the dissipative losses also increase. The PWM
controller must increase the duty cycle to compensate.
Eventually, one of two overload conditions will occur,
determined by V
due to the output load current. Either the maximum duty
cycle of 90% will be reached or the n-channel FET 1.2A
(nominal) peak current limit will be reached, which eff ec-
tively limits the duty cycle to a lower value. Above that
load, the output voltage will decrease rapidly and in
reverse order the startup current limits will be invoked as
the output voltage falls through its various voltage thresh-
olds. How far the output voltage drops depends on the
load voltage vs. current characteristic.
A reduction in input voltage, such as a discharging battery,
will lower the load current at which overload occurs.
Lower input voltage increases the duty cycle required to
produce a given output voltage. And lower input voltage
also increases the input current to maintain the input
power, which increases dissipative losses and further
increases the required duty cycle. Therefore an increase in
load current or a decrease in input voltage can result in
output overload. Please refer to the Max. I
Characteristics plots for the condition that best matches
the application.
IN
/V
OUT
OUT
–dependent startup current limit or duty
), but must be somewhat greater in prac-
IN
, V
OUT
, and the overall dissipative losses
OUT
OUT
vs. V
/R
LOAD
OUT
IN
Typical
. Note
, while
Once an overload has occurred, the load must be
decreased to permit recovery. The conditions required for
overload recovery are identical to those required for suc-
cessful initial startup.
Component Selection
The SC121 provides optimum performance when a 4.7μH
inductor is used with a 10μF output capacitor. Diff erent
component values can be used to modify input current or
output voltage ripple, improve transient response, or to
reduce component size or cost.
Inductor Selection
The inductance value primarily aff ects the amplitude of
inductor peak-to-peak current ripple (ΔI
inductance increases ΔI
current, I
current averaged over a full on/off cycle. I
the n-channel FET current limit I
the inductance may lower the output overload current
threshold. Increasing ΔI
minimum current, I
current threshold below which inductor negative–peak
current becomes zero.
Equating input power to output power and noting that
input current is equal to inductor current, average the
inductor current over a full PWM switching cycle to
obtain
where η is effi ciency.
Neglecting the n-channel FET R
for duty cycle D, and with T = 1/f
This is the change in I
off -state, again neglecting the p-channel FET R
the inductor DCR,
I
L
I
I
avg
L
L
on
off
L-max
1
L
1
L
1
= I
V
0
DT
DT
T
OUT
V
L-avg
V
V
IN
IN
IN
L-min
dt
I
OUT
+ ΔI
V
L
OUT
= I
V
during the on-state. During the
IN
L
L
L-avg
/2, where I
and raises the inductor peak
dt
L
L
D
– ΔI
also lowers the inductor
DS-ON
T
V
osc
LIM(N)
L
IN
/2, thus raising the load
,
and the inductor DCR,
V
, therefore reducing
L
L-avg
OUT
L-max
is the inductor
T
L
). Reducing
is subject to
1
SC121
DS-ON
D
and
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