CS5422GDWFR24 ON Semiconductor, CS5422GDWFR24 Datasheet
CS5422GDWFR24
Specifications of CS5422GDWFR24
Related parts for CS5422GDWFR24
CS5422GDWFR24 Summary of contents
Page 1
... IS+1 IS−1 V FB1 COMP1 A = Assembly Location WL Wafer Lot YY Year WW Work Week ORDERING INFORMATION Device Package CS5422GD16 SO−16 CS5422GDR16 SO−16 CS5422GDWF24 SO−24L CS5422GDWFR24 SO−24L 1 SO−16 D SUFFIX CASE 751B SO−24L DWF SUFFIX CASE 751E 16 GATE(H)2 GATE(L OSC IS+2 IS−2 V FB2 COMP2 24 GATE(H)2 ...
Page 2
Figure 1. Demonstration Circuit Schematic http://onsemi.com 2 ...
Page 3
ABSOLUTE MAXIMUM RATINGS* Operating Junction Temperature Storage Temperature Range ESD Susceptibility (Human Body Model) Package Thermal Resistance, SO−16: Junction−to−Case, R θJC Junction−to−Ambient, R θJA Package Thermal Resistance, SO−24L: Junction−to−Case, R θJC Junction−to−Ambient, R θJA Lead Temperature ...
Page 4
ELECTRICAL CHARACTERISTICS 10.8 V < V < 13.2 V; 10.8 V < BST < Characteristic Error Amplifier V Bias Current FB1(2) V Input Range FB1(2) COMP1,2 Source Current COMP1,2 Sink Current Reference Voltage 1(2) COMP1,2 Max ...
Page 5
ELECTRICAL CHARACTERISTICS (continued) 10.8 V < V < 13.2 V; 10.8 V < BST < Characteristic Supply Currents V Current CC BST Current Undervoltage Lockout Start Threshold Stop Threshold Hysteresis Hiccup Mode Overcurrent Protection OVC Comparator ...
Page 6
PACKAGE PIN DESCRIPTION PACKAGE PIN # SO−16 SO−24L − − − 5−8, 17− ...
Page 7
BIAS + − 8.6 V − 7.8 V IS+1 + − IS−1 − IS+2 − IS−2 − Set Dominant − 0.25 V − 5.0 μA ...
Page 8
THEORY OF OPERATION The CS5422 is a dual power supply controller that utilizes 2 the V control method. Two synchronous V can be built using a single controller. The fixed−frequency architecture, driven from a common oscillator, ensures a 180° phase ...
Page 9
PWM comparator terminates the initial pulse. 8.6 V 0.45 V UVLO STARTUP NORMAL OPERATION t S Figure 4. Idealized Waveforms Normal Operation During normal operation, the duty cycle of the gate drivers remains ...
Page 10
Figure 6. Hiccup Overcurrent Protection Output Enable On/Off control of the regulator outputs can be implemented by pulling the COMP pins low. The COMP pins must be driven below the 0.45 V PWM comparator offset voltage in order to disable ...
Page 11
R OSC (kW) Figure 8. Switching Frequency Selection of the Output Inductor The inductor should be selected based on its inductance, current capability, and DC resistance. Increasing the ...
Page 12
The voltage change during the load current transient is: ESL DV OUT + DI OUT ) ESR ) Dt where: / Δt = load current slew rate; ΔI OUT = load transient; ΔI OUT Δt = load transient duration time; ...
Page 13
Both logic level and standard FETs can be used. Voltage applied to the FET gates depends on the application circuit used. Both upper and lower gate driver outputs are specified to drive to within 1 ground when in ...
Page 14
Control IC Power Dissipation The power dissipation of the IC varies with the MOSFETs used and the CS5422 operating frequency. The CC average MOSFET gate charge current typically dominates the control IC power dissipation. The IC power dissipation ...
Page 15
CS5422−based regulator can be improved through the addition of a fixed amount of external slope compensation at the output of the PWM Error Amplifier (the COMP pin) during the regulator off−time. ...
Page 16
G K −T− SEATING PLANE 0.25 (0.010 −A− 24X 0.010 (0.25 −T− SEATING PLANE G 22X PACKAGE DIMENSIONS SO−16 D SUFFIX CASE ...
Page 17
... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...