SI8400AB-B-IS Silicon Laboratories Inc, SI8400AB-B-IS Datasheet - Page 6

• Manufacturer Part Number: SI8400AB-B-IS
• Description: IC ISOLATOR BIDIR I2C 8-SOIC
• Manufacturer: Silicon Laboratories Inc

Specifications of SI8400AB-B-IS

• Number Of Channels: 4
• Package / Case: 8-SOIC (3.9mm Width)
• Inputs - Side 1/side 2: 2/2
• Isolation Rating: 2500Vrms
• Voltage - Supply: 3 V ~ 5.5 V
• Data Rate: 10Mbps
• Output Type: Open Drain
• Operating Temperature: -40°C ~ 125°C
• Mounting Style: SMD/SMT
• Propagation Delay Time: 20 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current: 4.2 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Pin Count: 16
• Mounting: Surface Mount
• Package Type: SOIC W
• Screening Level: Automotive
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1765 - KIT EVAL FOR SI84XXISO
• Propagation Delay: -
• Lead Free Status / Rohs Status: Compliant

Si840x
Table 3. Si8400/01/02/05 Electrical Characteristics for Bidirectional I
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C unless otherwise noted.
6
Timing Specifications (Measured at 1.40 V Unless Otherwise Specified)
Maximum I
Propagation Delay
5 V Operation
Side A to side B rising
Side A to side B falling
Side B to side A rising
Side B to side A falling
3.3 V Operation
Side A to side B rising
Side A to side B falling
Side B to side A rising
Side B to side A falling
Pulse width distortion
5 V
Side A low to Side B low
Side B low to Side A low
3.3 V
Side A low to Side B low
Side B low to Side A low
Notes:
1. All voltages are relative to respective ground.
2. V
3. Logic low output voltages are 910 mV max from –10 to 125 °C at 3.0 mA.
4. I
5. Side A measured at 0.6 V.
Logic low output voltages are 955 mV max from –40 to 125 °C at 3.0 mA.
Logic low output voltages are 825 mV max from –10 to 125 °C at 0.5 mA.
Logic low output voltages are 875 mV max from –40 to 125 °C at 0.5 mA.
See “AN375: Design Considerations for Isolating an I
minimum difference between the output logic low level of the driving device and the input logic threshold.
2
IL
CV (Side A) = I
< 0.450 V, V
Parameter
2
C bus Frequency
IH
5
5
5
5
2
> 0.780 V.
CV
5
5
OL
(Side A) – I
Symbol
PWDAB
PWDBA
PWDAB
PWDBA
2
Tphab
Tphba
Tphab
Tphba
Fmax
Tplab
Tplba
Tplab
Tplba
CV
T
(Side A). To ensure no latch-up on a given bus, I
Rev. 1.3
2
C Bus or SMBus” for additional information.
No bus capacitance,
No bus capacitance,
Test Condition
See Figure 2
See Figure 2
R1 = 1400,
R1 = 1400,
R2 = 499,
R2 = 499,
R1 = 806,
R1 = 806
R2 = 499
R2 = 499
2
C Channels
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
2
CV (Side A) is the
Typ
9.0
9.0
25
15
20
28
13
20
10
15
—
11
11
1
(Continued)
Max
1.7
29
22
30
12
35
18
40
15
15
20
22
30
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns