LTM4600EV#PBF Linear Technology, LTM4600EV#PBF Datasheet - Page 9

• Manufacturer Part Number: LTM4600EV#PBF
• Description: IC DC/DC UMODULE 10A 104-LGA
• Manufacturer: Linear Technology
• Series: µModuler
• Type: Point of Load (POL) Non-Isolatedr

Specifications of LTM4600EV#PBF

• Design Resources: LTM4600 Spice Model
• Output: 0.6 ~ 5 V
• Number Of Outputs: 1
• Power (watts): 50W
• Mounting Type: Surface Mount
• Voltage - Input: 4.5 ~ 20V
• Package / Case: 104-LGA
• 1st Output: 0.6 ~ 5 VDC @ 10A
• Size / Dimension: 0.59" L x 0.59" W x 0.11" H (15mm x 15mm x 2.8mm)
• Power (watts) - Rated: 50W
• Operating Temperature: -40°C ~ 85°C
• Efficiency: 92%
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• 3rd Output: -
• 2nd Output: -

APPLICATIONS INFORMATION
The typical LTM4600 application circuit is shown in Figure
18. External component selection is primarily determined
by the maximum load current and output voltage.
Output Voltage Programming and Margining
The PWM controller of the LTM4600 has an internal
0.6V±1% reference voltage. As shown in the block dia-
gram, a 100k/0.5% internal feedback resistor connects
V
pin to SGND pin programs the output voltage:
Table 1 shows the standard values of 1% R
for typical output voltages:
Table 1.
Voltage margining is the dynamic adjustment of the output
voltage to its worst case operating range in production
testing to stress the load circuitry, verify control/protec-
tion functionality of the board and improve the system
reliability. Figure 2 shows how to implement margining
function with the LTM4600. In addition to the feedback
resistor R
Turn off both transistor Q
margining. When Q
voltage is margined up. The output voltage is margined
R
(kΩ)
OUT
(V)
V
SET
O
V
O
and V
= 0.6V •
Open
0.6
Figure 2. LTM4600 Margining Implementation
LTM4600
PGND
SET
OSET
, several external components are added.
100
1.2
100k + R
pins. Adding a resistor R
R
UP
66.5
SET
100k
1.5
SGND
is on and Q
SET
49.9
UP
1.8
V
V
OUT
OSET
and Q
43.2
2
DOWN
R
SET
DOWN
31.6
2.5
is off, the output
R
R
SET
DOWN
2N7002
UP
2N7002
to disable the
4600 F02
SET
Q
Q
from V
22.1
3.3
DOWN
UP
resistor
OSET
13.7
5
down when Q
voltage V
resistor values of R
the following equations:
Input Capacitors
The LTM4600 μModule should be connected to a low
ac-impedance DC source. High frequency, low ESR input
capacitors are required to be placed adjacent to the mod-
ule. In Figure 18, the bulk input capacitor C
for its ability to handle the large RMS current into the
converter. For a buck converter, the switching duty-cycle
can be estimated as:
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
In the above equation, η% is the estimated effi ciency of
the power module. C1 can be a switcher-rated electrolytic
aluminum capacitor, OS-CON capacitor or high volume
ceramic capacitors. Note the capacitor ripple current
ratings are often based on only 2000 hours of life. This
makes it advisable to properly derate the input capacitor,
or choose a capacitor rated at a higher temperature than
required. Always contact the capacitor manufacturer for
derating requirements.
In Figure 18, the input capacitors are used as high fre-
quency input decoupling capacitors. In a typical 10A
output application, 1-2 pieces of very low ESR X5R or
X7R, 10μF ceramic capacitors are recommended. This
decoupling capacitor should be placed directly adjacent
I
D =
(R
R
CIN(RMS)
SET
R
SET
(R
SET
V
V
IN
SET
O
+ (100k
O
R
• V
needs to be margined up/down by ±M%, the
UP
=
R
O
) • V
I
DOWN
UP
O(MAX)
• (1– M%)
) + 100k
%
O
UP
R
• (1+ M%)
is on and Q
DOWN
and R
• D • (1 D)
)
DOWN
= 0.6V
= 0.6V
UP
can be calculated from
is off. If the output
LTM4600
IN
is selected
4600fc
9