KSZ8851SNL-BBE-EVAL Micrel Inc, KSZ8851SNL-BBE-EVAL Datasheet - Page 41

BOARD EVAL MAC/PHY FOR KSZ8851

KSZ8851SNL-BBE-EVAL

Manufacturer Part Number
KSZ8851SNL-BBE-EVAL
Description
BOARD EVAL MAC/PHY FOR KSZ8851
Manufacturer
Micrel Inc
Series
LinkMD®r

Specifications of KSZ8851SNL-BBE-EVAL

Design Resources
BeagleBoard Zippy2
Main Purpose
Interface, Ethernet Controller (PHY and MAC)
Embedded
No
Utilized Ic / Part
KSZ8851SNL
Primary Attributes
1 Port, 100BASE-TX/10BASE-T
Secondary Attributes
SPI Interface, LinkMD Cable Diagnostics
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
576-3602
KSZ8851SNL-BBE-EVL
ZIPPY2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KSZ8851SNL-BBE-EVAL
Manufacturer:
Micrel Inc
Quantity:
135
MARH[15:0] = 0x0123
Host MAC Address Register Low (0x10 – 0x11): MARL
The following table shows the register bit fields for Low word of Host MAC address.
Host MAC Address Register Middle (0x12 – 0x13): MARM
The following table shows the register bit fields for middle word of Host MAC address.
Host MAC Address Register High (0x14 – 0x15): MARH
The following table shows the register bit fields for high word of Host MAC address.
0x16 – 0x1F: Reserved
On-Chip Bus Control Register (0x20 – 0x21): OBCR
This register controls the on-chip bus clock speed for the KSZ8851SNL. The default of the on-chip bus clock speed is 125
MHz. When the external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best
performance.
August 2009
Micrel, Inc.
Bit
15-0
Bit
15-0
Bit
15-0
Bit
15-7
6
5-3
2
1-0
-
-
-
-
0
0
Default Value
Default Value
Default Value
Default Value
0x0
0x0
R/W
RW
R/W
RW
R/W
RW
R/W
RO
RW
RO
RW
RW
Description
MARL MAC Address Low
The least significant word of the MAC address.
Description
MARM MAC Address Middle
The middle word of the MAC address.
Description
MARH MAC Address High
The Most significant word of the MAC address.
Description
Reserved
Output Pin Drive Strength
Bi-directional or output pad drive strength selection.
0: 8 mA
1: 16 mA
Reserved
On-Chip Bus Clock Selection
0: 125 MHz (default setting is divided by 1, Bit[1:0]=00)
1: NA (reserved)
On-Chip Bus Clock Divider Selection
00: Divided by 1.
01: Divided by 2.
10: Divided by 3.
11: NA (reserved).
For example to contol the bus clock speed as below:
If Bit 2 = 0 and this value is set 00 to select 125 MHz.
If Bit 2 = 0 and this value is set 01 to select 62.5 MHz.
41
KSZ8851SNL/SNLI
M9999-083109-2.0

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