CDB5460AU Cirrus Logic Inc, CDB5460AU Datasheet - Page 6

• Manufacturer Part Number: CDB5460AU
• Description: EVALUATION BOARD FOR CS5460A
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5460AU

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS5460A
• Primary Attributes: 1-Phase Current & Voltage Monitoring
• Secondary Attributes: Graphical User Interface, SPI™ & USB Interfaces
• Processor To Be Evaluated: CS5460A, C8051F320
• Interface Type: USB
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

ANALOG CHARACTERISTICS
Notes: 7. The minimum FSCR is limited by the maximum allowed gain register value.
6
Dynamic Characteristics
Phase Compensation Range
High Rate Filter Output Word Rate
Input Sample Rate
Full Scale DC Calibration Range
Channel-to-Channel Time-Shift Error
(when PC[6:0] bits are set to “0000000”)
High Pass Filter Pole Frequency
Power Supplies
Power Supply Currents (Active State)
Power Consumption
(Note 8)
Power Supply Rejection Ratio
for Current Channel
(Note 9)
Power Supply Rejection Ratio
for Voltage Channel
PFMON Power-Fail Detect Threshold
PFMON “Power-Restored” Detect Threshold
10. When voltage level on PFMON is sagging, and LSD bit is 0, the voltage at which LSD bit is set to 1.
11. Assuming that the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), then if/when
8. All outputs unloaded. All inputs CMOS level.
9. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV zero-to-peak sinewave
(frequency = 60 Hz) is imposed onto the +5 V supply voltage at VA+ and VD+ pins. The “+” and “-” input
pins of both input channels are shorted to VA-. Then the CS5460A is commanded to ’continuous
computation cycles’ data acquisition mode, and digital output data is collected for the channel under
test. The zero-peak value of the digital sinusoidal output signal is determined, and this value is
converted into the zero-peak value of the sinusoidal voltage that would need to be applied at the
channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as
Veq. PSRR is then (in dB):
the PFMON voltage starts to rise again, PMHI is the voltage level (on PFMON pin) at which the LSD bit
can be permanently reset back to 0 (without instantaneously changing back to 1). Attempts to reset the
LSD bit before this condition is true will not be successful. This condition indicates that power has been
restored. Typically, for a given sample, the PMHI voltage will be ~100 mV above the PMLO voltage.
Parameter
Active State (VD+ = 3.3 V)
(Voltage Channel, 60 Hz)
Active State (VD+ = 5 V)
I
DCLK = MCLK/K
D+
(Both Channels)
I
Stand-By State
D+
(VD+ = 3.3 V)
PSRR
(VD+ = 5 V)
(Continued)
Sleep State
(Gain = 10)
(Gain = 50)
(50, 60 Hz)
(50, 60 Hz)
(Note 10)
(Note 11)
(Note 7)
(Note 9)
=
-3 dB
20
I
A+
⋅
log
Symbol
⎧
⎨
⎩
FSCR
PSCA
PSCD
PSCD
PSRR
PSRR
PSRR
PMLO
PMHI
OWR
0.150V
------------------ -
PC
V
eq
⎫
⎬
⎭
Min
-2.4
2.3
25
56
75
-
-
-
-
-
-
-
-
-
-
-
-
DCLK/1024
DCLK/8
6.75
2.45
2.55
11.6
Typ
1.0
0.5
1.3
2.9
1.7
21
10
65
-
-
-
-
Max
+2.5
100
2.7
CS5460A
25
-
-
-
-
-
-
-
-
-
-
-
-
-
DS487F4
%F.S.
Unit
mW
mW
mW
Sps
Sps
mA
mA
mA
µW
Hz
dB
dB
dB
µs
V
V
°