CY3687 Cypress Semiconductor Corp, CY3687 Datasheet
CY3687
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... D– XCVR Integrated Full- and High-Speed XCVR Enhanced USB Core Simplifies 8051 Code Cypress Semiconductor Corporation Document # 001-06120 Rev *J MoBL-USB™ FX2LP18 USB ■ Integrated, Industry Standard Enhanced 8051 ❐ 48 MHz, 24 MHz MHz CPU operation ❐ Four clocks per instruction cycle ❐ ...
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Contents Applications ...................................................................... 3 Functional Overview ........................................................ 3 USB Signaling Speed .................................................. 3 8051 Microprocessor ................................................... C™ Bus .................................................................... 4 Buses .......................................................................... 4 USB Boot Methods ...................................................... 4 ReNumeration™ .......................................................... 4 Bus-Powered Applications .......................................... 4 Interrupt System ...
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... Cypress Semiconductor Corporation’s MoBL-USB™ FX2LP18 (CY7C68053 low voltage (1.8 V) version of the EZ-USB FX2LP (CY7C68013A), which is a highly integrated, low power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, ...
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Table 1. Special Function Registers IOA IOB 1 SP EXIF 2 DPL0 MPAGE 3 DPH0 4 DPL1 5 DPH1 6 DPS 7 PCON 8 TCON SCON0 9 TMOD SBUF0 A TL0 AUTOPTRH1 B TL1 AUTOPTRL1 C ...
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If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP18 substitutes its INT2VEC byte. Therefore, if the high byte (‘page’ jump-table address is preloaded at Table 2. INT2 USB Interrupts Priority INT2VEC Value 1 00 ...
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Figure 2. Reset Timing Plots RESET RESET Power on Reset 3.9 Reset and Wakeup The reset and wakeup pins are described in detail in this section. 3.9.1 Reset Pin The input pin, RESET#, resets the FX2LP18 when ...
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CTL0-2. If tri-stated via GPIFIDLECTL, these pins must be pulled GND or driven by another chip. CC_IO ■ RESET#, WAKEUP#. These pins must be pulled to V GND or driven by another chip during suspend. Figure ...
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Endpoint Configurations (High Speed Mode) Endpoints 0 and 1 are the same for every configuration. Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either BULK or INTERRUPT. The endpoint buffers can be configured in any ...
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Default High Speed Alternate Settings Table 5. Default High Speed Alternate Settings Alternate Setting 0 ep0 64 ep1out 0 ep1in 0 ep2 0 ep4 0 ep6 0 ep8 0 3.13 External FIFO Interface The architecture, control signals, and clock ...
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Three Control OUT Signals The 56-pin package brings out three of these signals, CTL0–CTL2. The 8051 programs the GPIF unit to define the CTL waveforms. CTLx waveform edges can be programmed to make transitions as fast as once per ...
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Table 6. Strap Boot EEPROM Address Lines to These Values Bytes Example EEPROM A2 [8] 16 24AA00 N/A 128 24AA01 0 256 24AA02 0 4K 24AA32 0 8K 24AA64 0 16K 24AA128 0 2 3.18 Interface Boot Load ...
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Figure 7. CY7C68053 56-pin VFBGA Pin Assignment - Top View Document # 001-06120 Rev * ...
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CY7C68053 Pin Descriptions [9] Table 7. FX2LP18 Pin Descriptions 56 VFBGA Name Type 2D AV Power Power CC 2F AGND Ground 1F AGND Ground 1E DMINUS I/O/Z 2E DPLUS I/O/Z 8B RESET# Input 1C XTALIN Input ...
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Table 7. FX2LP18 Pin Descriptions (continued) 56 VFBGA Name Type 6F PA4 or I/O/Z FIFOADR0 8C PA5 or I/O/Z FIFOADR1 7C PA6 or I/O/Z PKTEND 6C PA7 or I/O/Z FLAGD or SLCS# Port B 3H PB0 or I/O/Z FD[0] 4F ...
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Table 7. FX2LP18 Pin Descriptions (continued) 56 VFBGA Name Type PORT D 8A PD0 or I/O/Z FD[8] 7A PD1 or I/O/Z FD[9] 6B PD2 or I/O/Z FD[10] 6A PD3 or I/O/Z FD[11] 3B PD4 or I/O/Z FD[12] 3A PD5 or ...
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Table 7. FX2LP18 Pin Descriptions (continued) 56 VFBGA Name Type 7B WAKEUP Input 3F SCL OD 3G SDA Power CC_IO 5B V Power CC_IO 7E V Power CC_IO 8E V Power CC_IO 5C V Power CC_D 1G ...
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Register Summary FX2LP18 register bit definitions are described in the MoBL-USB FX2LP18 TRM in greater detail. Table 8. FX2LP18 Register Summary Hex Size Name Description GPIF Waveform Memories E400 128 WAVEDATA GPIF Waveform descriptor data ...
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Table 8. FX2LP18 Register Summary (continued) Hex Size Name Description E62C 1 ECC1B2 ECC1 Byte 2 address E62D 1 ECC2B0 ECC2 Byte 0 address E62E 1 ECC2B1 ECC2 Byte 1 address E62F 1 ECC2B2 ECC2 Byte 2 address [10] E630 ...
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Table 8. FX2LP18 Register Summary (continued) Hex Size Name Description E65E 1 EPIE Endpoint interrupt enables [11] E65F 1 EPIRQ Endpoint interrupt requests [10] E660 1 GPIFIE GPIF interrupt enable [10] E661 1 GPIFIRQ GPIF interrupt request E662 1 USBERRIE ...
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Table 8. FX2LP18 Register Summary (continued) Hex Size Name Description E6A2 1 EP1INCS Endpoint 1 IN control and status E6A3 1 EP2CS Endpoint 2 control and status E6A4 1 EP4CS Endpoint 4 control and status E6A5 1 EP6CS Endpoint 6 ...
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Table 8. FX2LP18 Register Summary (continued) Hex Size Name Description Reserved [10] E6D2 1 EP2GPIFFLGSEL Endpoint 2 GPIF flag select E6D3 1 EP2GPIFPFSTOP Endpoint 2 GPIF stop trans- action on program flag [10] E6D4 1 EP2GPIFTRIG Endpoint 2 GPIF trigger ...
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Table 8. FX2LP18 Register Summary (continued) Hex Size Name Description Special Function Registers (SFRs) [13 IOA Port A (bit addressable Stack Pointer 82 1 DPL0 Data Pointer DPH0 Data Pointer 0 ...
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Table 8. FX2LP18 Register Summary (continued) Hex Size Name Description [13 SCON1 Serial Port 1 Control (bit addressable) [13 SBUF1 Serial Port 1 Data Buffer C2 6 Reserved C8 1 T2CON Timer/Counter 2 Control (bit addressable) ...
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Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature................................... –65°C to +150°C Ambient temperature with power supplied Industrial ....................................................... –40°C to +85°C Supply voltage to ground potential ...
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Table 9. DC Characteristics Parameter Description I Supply current (AV ) CC_AVcc CC I Supply current (V ) CC_IO CC_IO I Supply current (V CC_CORE CC_CORE T Reset time after valid power RESET Pin reset after powered ...
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Table 11. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK Parameter [18] t IFCLK period IFCLK t RDY to clock setup time SRY X t Clock to RDY RYH X t GPIF data to clock setup time SGD t ...
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Table 13. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK Parameter t IFCLK period IFCLK t SLRD to clock setup time SRD t Clock to SLRD hold time RDH t SLOE turn-on to FIFO data valid OEon t SLOE ...
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Slave FIFO Synchronous Write Figure 11. Slave FIFO Synchronous Write Timing Diagram IFCLK SLWR DATA Z FLAGS Table 15. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK Parameter t IFCLK period IFCLK t SLWR to clock setup time ...
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Slave FIFO Asynchronous Write Figure 12. Slave FIFO Asynchronous Write Timing Diagram SLWR DATA FLAGS Table 17. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK Parameter t SLWR pulse LOW WRpwl t SLWR pulse HIGH WRpwh t SLWR ...
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There is no specific timing requirement to be met for asserting the PKTEND pin with regards to asserting SLWR. PKTEND can be asserted with the last data value clocked into the FIFOs or thereafter. The only consideration is that the ...
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Slave FIFO Output Enable Figure 16. Slave FIFO Output Enable Timing Diagram SLOE DATA Table 21. Slave FIFO Output Enable Parameters Parameter t SLOE assert to FIFO data output OEon t SLOE deassert to FIFO data hold OEoff 9.10 ...
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Slave FIFO Synchronous Address Figure 18. Slave FIFO Synchronous Address Timing Diagram IFCLK SLCS/FIFOADR [1:0] Table 23. Slave FIFO Synchronous Address Parameters Parameter t Interface clock period IFCLK t FIFOADR[1:0] to clock setup time SFA t Clock to FIFOADR[1:0] ...
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Sequence Diagram Various sequence diagrams and examples are presented in this section. 9.13.1 Single and Burst Synchronous Read Example Figure 20. Slave FIFO Synchronous Read Sequence and Timing Diagram t IFCLK IFCLK t SFA FIFOADR t=0 t SRD SLRD ...
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Single and Burst Synchronous Write Figure 22. Slave FIFO Synchronous Write Sequence and Timing Diagram t IFCLK IFCLK t SFA FIFOADR t=0 t SWR SLWR t=2 t=3 SLCS FLAGS t t FDH SFD N DATA t=1 PKTEND Figure 22 ...
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Sequence Diagram of a Single and Burst Asynchronous Read Figure 23. Slave FIFO Asynchronous Read Sequence and Timing Diagram t t SFA FAH FIFOADR t RDpwl RDpwh SLRD t=3 t=2 SLCS t XFLG FLAGS t XFD Data ...
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Sequence Diagram of a Single and Burst Asynchronous Write Figure 25. Slave FIFO Asynchronous Write Sequence and Timing Diagram t t SFA FAH FIFOADR t WRpwl WRpwh SLWR t =1 t=3 SLCS t XFLG FLAGS t t ...
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... For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Table 24. Key Features and Ordering Information Ordering Code CY7C68053-56BAXI Development Tool Kit CY3687 Ordering Code Definitions XXXX - 56BAX (C, I) ...
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Package Diagram The FX2LP18 is available in a 56-pin VFBGA package. Figure 26. 56 VFBGA (5 × 5 × 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 Document # 001-06120 Rev *J CY7C68053 001-03901 *C [+] Feedback [+] Feedback Page ...
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PCB Layout Recommendations The following recommendations must be followed to ensure reliable high performance operation. ■ At least a four-layer impedance controlled board is required to maintain signal quality. ■ Specify impedance targets (ask your board vendor what they ...
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Acronyms Table 25. Acronyms Used in this Document Acronym Description ATA advanced technology attachment ASIC application specific integrated circuit CPU central processing unit DID device identifier DSP digital signal processor EEPROM electrically erasable programmable read only memory EPP enhanced ...
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Document History Page Document Title: CY7C68053 MoBL-USB™ FX2LP18 USB Microcontroller Document Number: 001-06120 Orig. of Submission Revision ECN Change ** 430449 OSG 03/03/06 *A 434754 OSG 03/24/06 *B 465471 OSG See ECN *C 484726 ARI See ECN *D 492009 OSG ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...