MAX9860EVKIT+ Maxim Integrated Products, MAX9860EVKIT+ Datasheet - Page 20

• Manufacturer Part Number: MAX9860EVKIT+
• Description: KIT EVALUATION FOR MAX9860
• Manufacturer: Maxim Integrated Products

Specifications of MAX9860EVKIT+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-Bit Mono Audio Voice Codec
Table 5. Digital Audio Interface Registers (continued)
20
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ADLY
BSEL
BITS
ST
ADC Delay Mode
0 = SDOUT data is valid on the first BCLK edge following an LRCLK edge.
1 = SDOUT data is delayed one BCLK cycle so that it is valid on the 2nd BCLK edge following an
ADLY is ignored when TDM = 1.
Stereo Enable
0 = The interface transmits and receives only one channel of data. If right record path is enabled, no
1 = The interface operates in stereo. The left and right incoming data are summed to mono and then
BCLK Select
Configures BCLK when operating in master mode. BSEL has no effect in slave mode. Set BSEL = 010,
unless sharing the bus with multiple devices.
000 = Off
001 = 64x LRCLK (192x internal clock divided by 3)
010 = 48x LRCLK (192x internal clock divided by 4)
011 = Reserved for future use.
100 = PCLK/2
101 = PCLK/4
110 = PCLK/8
111 = PCLK/16
LRCLK edge (I
data from this channel is transmitted.
routed to the DAC. The summed data is divided by 2 to prevent overload. Both the left and right
record signals are transmitted.
2
S-compatible mode).
FUNCTION