DS3170DK Maxim Integrated Products, DS3170DK Datasheet
DS3170DK
Specifications of DS3170DK
Related parts for DS3170DK
DS3170DK Summary of contents
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... GENERAL DESCRIPTION The DS3170DK is a fully integrated design kit for the DS3170 DS3/E3 single-chip transceiver (SCT). This design kit contains all the necessary circuitry to evaluate the DS3170 in all modes of operation. The design kit also includes an on-board microprocessor to run real-time code for further part evaluation. ...
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COMPONENT LIST DESIGNATION QTY C1, C4, C5, C10, C14, C15, C18, C19, C21, C24, C25–C32, C36- C38, C39–C44, 44 C47–C49, C50, C52–C56, C59–C61, C66, C68, C70, C73, C74 C2, C3, C16, C17, C20, C22, C23, 13 C33, C34, C51, C57, ...
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DESIGNATION QTY R1–R4, R12, R42, R43, R54–R56, R59, R63, R68, 20 150Ω 1%, 1/16W resistors (0603) R69, R70, R73, R74, R83, R93, R107 R5–R8, R10, R15, R51, R57, R62, R71, R81, R85, 22 33Ω 5%, 1/16W resistors (0603) R92, R94, ...
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... GENERAL- PURPOSE ADDRESS/CS DECODE VDD DS3170 TEST POINTS VCC SRAM BOARD GND SRAM BOARD RST DS3170 RST BOARD DS3170DK DS3/E3 Single-Chip Transceiver Design Kit DESCRIPTION Xilinx Toshiba Toshiba Maxim Dove Electronic SaRonix SaRonix SaRonix JTAG OSC CONTROL STS1 TEST POINTS FPGA ...
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... DIP switches (SW3) can be in either the ON or OFF position depending on the desired configuration. See Table 6.. • Connect serial cable from DS3170DK (J2) to PC. • Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. Reference Clock Configuration The reference clock for the DS3170 (SCT) can be configured a number of ways depending on the application's need ...
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... JTDO Address/Data BUS Connector The DS3170DK has a connector (J3) to monitor all local bus activity for the design kit. All the signals can be captured with a high-impedance probe and displayed on an oscilloscope or logic analyzer. Note: If FPGA_ENABLE (SW3.3) is logic 0, the on-board microcontroller will no longer drive any data onto the local bus. Therefore, the user can now connect the local bus of the DS3170 into another system without making any modifications to the hardware ...
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High Impedance and Compensated Test Points The test points for all the clock and data lines are unique for this board such that each test point listed in have a relative high-impedance pin and a compensated pin. The compensated pin ...
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... The second input type for the GPIO port is a straight 10-pin header (J7). This can be simply a monitoring pin for the GPIO port or used as input stimulus. Note: If you plan to drive a bit to a value other than GND, the GPIO bit in SW4 must be in the “Off” position. See the DS3170DK schematic for questions on the connection of the GPIO port. Table 4 provides a description of pin out of SW4 and J7 ...
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User Input Switch (SW3) SW3 is an 8-pin DIP switch that controls the function of the on-board microcontroller and the two on-board FPGAs, and offers a number of generic inputs for user programs. Table 6. User Input Switch Pinout PIN ...
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... Start button on the Windows toolbar and select Programs → ChipView → ChipView. • Load the DS3170DK.DEF file. • Make sure that all the register settings are correct for the proper function desired for the DS3170DK. • Refer to the DS3170 data sheet for all questions pertaining to device functionality. MEMORY MAP The on-board microcontroller is configured to start the user address space at 0x81000000 ...
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CONTROL REGISTERS Register Name: CTRL1 Register Description: Control Register 1 Register Offset: 0x0008 Bit # 7 Name SPI_CPOL SPI_CPHA Default 0 Bit 7: SPI_CPOL: This bit controls the SPI Interface Clock Polarity pin, which is muxed with the D7 pin ...
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Register Name: CTRL2 Register Description: Control Register 2–Line IO Register Offset: 0x0009 Bit # 7 6 Name RNEG3 RNEG2 Default 0 0 Bits RNEGx: These bits control the source of the RNEG signal. Bits ...
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Register Name: CTRL3 Register Description: Control Register 3–Line RCLK Register Offset: 0x000A Bit # 7 6 Name — — Default 0 0 Bits These bits are unused. Bits RLCLKx: These bits control the source ...
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Register Name: CTRL4 Register Description: Control Register 4 Overhead Interface Register Offset: 0x000B Bit # 7 6 Name TOHEN3 TOHEN2 Default 0 0 Bits TOHENx: These bits control the source of the TOHEN signal. Bits 3 to ...
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Register Name: CTRL5 Register Description: Control Register 5 Serial Data Overhead Interface Register Offset: 0x000C Bit # 7 6 Name — — Default 0 0 Bits These bits are unused. Bits TSERx: These bits ...
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Register Name: CTRL6 Register Description: Control Register 6 Serial Data Overhead Interface Register Offset: 0x000D Bit # 7 6 Name TSOFI3 TSOFI2 Default 0 0 Bits TSOFIx: These bits control the source of the TSOFI signal. Bits ...
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... For more information about the DS3170, refer to the DS3170 data sheet available on our website at ic.com/DS3170. Software downloads are also available for this design kit. DS3170DK INFORMATION For more information about the DS3170DK including software downloads, consult the DS3170DK data sheet available on our website at www.maxim-ic.com/DS3170DK. TECHNICAL SUPPORT For additional technical support, e-mail your questions to telecom ...
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