CDB5368 Cirrus Logic Inc, CDB5368 Datasheet - Page 16

• Manufacturer Part Number: CDB5368
• Description: BOARD EVAL FOR CS5368 192KHZ ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5368

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Inputs Per Adc: 8 Differential
• Input Range: ±0.3 V
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5368
• Description/function: Audio A/D
• Operating Supply Voltage: 3.3 V
• Product: Audio Modules
• For Use With/related Products: CS5368
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1157

16
SERIAL AUDIO INTERFACE - TDM TIMING
The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.
Logic "0" = GND = 0 V; Logic "1" = VLS; C
Notes:
Sample Rates
Master Mode
SCLK Frequency
SCLK Period
SCLK Duty Cycle
FS setup
FS setup
FS setup
FS width
SDOUT setup
SDOUT hold
Slave Mode
SCLK Frequency
SCLK Period
SCLK Duty Cycle
FS setup
FS setup
FS setup
FS width
SDOUT setup
SDOUT hold
SDOUT
1. TDM Quad-Speed Mode only specified to operate correctly at VLS ≥ 3.14 V.
2. Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under
3. CLKMODE functionality described in
4. In Slave Mode, the SCLK/LRCK ratio can be set according to preference; chip performance is guaran-
SCLK
FS
Clocking” on page
teed only when using the ratios in
(Note 4)
(Note 2)
before SCLK rising (Double-Speed Mode)
before SCLK rising (Double-Speed Mode)
before SCLK rising (Single-Speed Mode)
before SCLK rising (Single-Speed Mode)
before SCLK rising (Quad-Speed Mode)
before SCLK rising (Quad-Speed Mode)
data
Parameter
10.
(CLKMODE =
(CLKMODE =
Double-Speed Mode
Quad-Speed Mode
Single-Speed Mode
t
before SCLK rising
before SCLK rising
PERIOD
after SCLK rising
after SCLK rising
1/(256*216 kHz)
1/(256*216 kHz)
in SCLK cycles
in SCLK cycles
L
= 20 pF, timing threshold is 50% of VLS.
t
0)(Note 3)
1)(Note 3)
SETUP2
Section 4.7 Master and Slave Clock Frequencies on page
Figure 4. TDM Timing
t
SETUP1
Section 4.6.3
1
data
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
SETUP1
SETUP1
SETUP1
SETUP2
SETUP1
SETUP1
SETUP1
SETUP2
PERIOD
t
t
t
PERIOD
t
t
HOLD2
HOLD2
HIGH1
HIGH1
HIGH2
HIGH1
HIGH2
new frame
t
HOLD2
-
-
-
t
HIGH1
"Master Mode Clock Dividers" on page
t
HIGH2
256*Fs
Min
108
128
54
18
40
28
20
18
18
28
20
20
10
2
5
5
5
1
5
5
-
256*Fs
Typ
50
33
data
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
256*Fs
Max
108
216
128
244
54
60
38
65
-
-
-
-
-
-
-
-
-
-
-
-
-
CS5368
DS624F4
25.
24.
“System
Unit
kHz
kHz
kHz
Hz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%
-
-