AD9445BB-LVDS/PCBZ Analog Devices Inc, AD9445BB-LVDS/PCBZ Datasheet
AD9445BB-LVDS/PCBZ
Specifications of AD9445BB-LVDS/PCBZ
Related parts for AD9445BB-LVDS/PCBZ
AD9445BB-LVDS/PCBZ Summary of contents
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FEATURES 125 MSPS guaranteed sampling rate (AD9445BSV-125) 78.3 dBFS SNR/92 dBFS SFDR with 30 MHz input (3.2 V p-p) 74.8 dBFS SNR/95 dBFS SFDR with 30 MHz input (2.0 V p-p) 77.0 dBFS SNR/87 dBFS SFDR with 170 MHz input ...
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AD9445 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 6 Switching ...
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SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 2.0 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = −1.0 dBFS, DCS on, unless otherwise ...
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AD9445 AC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 2.0 V p-p differential input, internal trimmed reference (1.0 V mode −1.0 dBFS, DCS on, RF ENABLE ...
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Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR, Second or Third Harmonic MHz MHz 170 MHz 225 MHz 300 MHz 400 ...
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AD9445 DIGITAL SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3 Table 3. Parameter CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE) High Level Input Voltage Low Level Input Voltage High Level Input Current Low ...
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TIMING DIAGRAMS N – CLKL t CLKH CLK+ CLK– DATA OUT DCO+ DCO– t CPD N N – 1 VIN t CLKL t CLKH CLK– CLK DCO+ DCO– ...
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AD9445 ABSOLUTE MAXIMUM RATINGS Table 5. With Respect To Parameter ELECTRICAL AVDD1 AGND AVDD2 AGND DRVDD DGND AGND DGND AVDD1 DRVDD AVDD2 DRVDD AVDD2 AVDD1 D0± to D13± DGND CLK+/CLK− AGND OUTPUT MODE, DCS AGND MODE, DFS, SFDR, RF ENABLE ...
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TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay ( The delay between the 50% ...
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AD9445 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 DCS MODE DNC 2 OUTPUT MODE 3 DFS 4 LVDS_BIAS 5 AVDD1 6 SENSE 7 VREF 8 AGND 9 REFT 10 REFB 11 AVDD2 12 AVDD2 13 AVDD2 14 AVDD2 15 AVDD2 16 ...
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Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode Pin No. Mnemonic 1 DCS MODE DNC 3 OUTPUT MODE 4 DFS 5 LVDS_BIAS 20 34, 36, 38, AVDD1 43 to 45, ...
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AD9445 Pin No. Mnemonic 83 D12− 84 D12+ 85 D13− 86 D13+ (MSB) 89 OR− 90 OR+ 100 RF ENABLE Description D12 Complement Output Bit. D12 True Output Bit. D13 Complement Output Bit. D13 True Output Bit. Out-of-Range Complement Output ...
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DCS MODE 1 PIN 1 DNC 2 OUTPUT MODE 3 DFS 4 LVDS_BIAS 5 AVDD1 ...
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AD9445 Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode Pin No. Mnemonic 1 DCS MODE 62 66 DNC 3 OUTPUT MODE 4 DFS 5 LVDS_BIAS 20 ...
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EQUIVALENT CIRCUITS AVDD2 VIN+ 1k Ω 6pF X1 3.5V 1k Ω AVDD2 VIN– 6pF Figure 6. Equivalent Analog Input Circuit DRVDD 1.2V LVDS_BIAS 3.74k Ω Figure 7. Equivalent LVDS_BIAS Circuit DRVDD V DX– V Figure 8. Equivalent LVDS Digital Output ...
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AD9445 TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, rated sample rate, LVDS mode, DCS enabled, T input, AIN = −1.0 dBFS, internal trimmed reference (nominal VREF = 1.0 V), unless otherwise noted. ...
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SFDR +85°C 95 SFDR +25°C 90 SFDR –40°C 85 SNR +25°C SNR –40° SNR +85° 100 150 200 250 300 350 ANALOG INPUT FREQUENCY (MHz) Figure 18. AD9445-125 SNR/SFDR vs. Analog ...
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AD9445 0 105MSPS –10 30.3MHz @ –1.0dBFS SNR = 74.3dB –20 ENOB = 12.2BITS SFDR = 92dBc –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 13.125 26.250 FREQUENCY (MHz) Figure 24. AD9445-105 64k Point Single-Tone FFT/105 ...
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SFDR +25°C SFDR –40° SFDR +85° SNR –40° SNR +85°C SNR +25° 100 150 200 250 300 350 ANALOG INPUT FREQUENCY (MHz) Figure 30. AD9445-105 SNR/SFDR vs. Analog ...
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AD9445 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 13.625 27.250 FREQUENCY (MHz) Figure 36. AD9445-125 64k Point Two-Tone FFT/ 125 MSPS/30.3 MHz, 31.3 MHz 0 –10 –20 SFDR dBc –30 –40 ...
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N – – – – OUTPUT CODE Figure 42. AD9445-125 Grounded ...
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AD9445 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0 4096 8192 OUTPUT CODE Figure 48. AD9445-125 DNL Error vs. Output Code, 125 MSPS, 10.3 MHz 1.014 1.012 1.010 1.008 1.006 1.004 1.002 –40 – TEMPERATURE ...
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SFDR dBc 76 75 225.3MHz SFDR dBc 74 300.3MHz SFDR dBc 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 ANALOG INPUT RANGE (V p-p) Figure 54. AD9445-105 SNR vs. Analog Input Range, 105 MSPS/170.3 ...
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AD9445 THEORY OF OPERATION The AD9445 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated, high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 14-bit pipeline ADC core. The ...
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External Reference Operation The AD9445’s internal reference is trimmed to enhance the gain accuracy of the ADC. An external reference may be more stable over temperature, but the gain of the ADC is not likely to improve. Figure 49 shows ...
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AD9445 CLOCK INPUT CONSIDERATIONS Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is ...
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INPUT FREQUENCY (MHz) Figure 66. SNR vs. Input Frequency and Jitter POWER CONSIDERATIONS Care should be taken when selecting a power source. The use of linear dc supplies is ...
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AD9445 OPERATIONAL MODE SELECTION Data Format Select The data format select (DFS) pin of the AD9445 determines the coding format of the output data. This pin is 3.3 V CMOS- compatible, with logic high (or AVDD1, 3.3 V) selecting twos ...
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EVALUATION BOARD Evaluation boards are offered to configure the AD9445 in either CMOS or LVDS mode only. This design represents a recommended configuration for using the device over a wide range of sampling rates and analog input frequencies. These evaluation ...
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AD9445 1 P1 XTALPWR 2 P2 EXTREF 3 P3 DRGND 4 P4 DRVDD 1 P1 GND 2 P2 VCC 3 P3 GND MTHOLE6 DRVDD D11_C/D6_Y H3 D11_T/D7_Y MTHOLE6 D12_C/D8_Y D12_T/D9_Y H1 D13_C/D10_Y MTHOLE6 D13_T/D11_Y GND D14_C/D12_Y ...
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CR1 CR2 Figure 68. AD9445 Evaluation Board Schematic (Continued) Rev Page AD9445 ...
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AD9445 BYPASS CAPACITORS VCC + C64 C43 10μF 0.1μF GND VCC C11 XX GND DRVDD + C65 C47 C23 10μF 0.1μF 0.1μF DRGND 5V + C56 C85 10μF 0.1μF GND 5V GND 5V GND C35 C32 C30 C28 C27 C90 ...
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Figure 70. AD9445 Evaluation Board Schematic (Continued) Rev Page AD9445 ...
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AD9445 Table 11. AD9445-125 Baseband Customer Evaluation Board Bill of Materials Item Qty. Reference Designator 1 7 C4, C6, C33, C34, C87, C88, C89 2 44 C2, C3, C5, C7, C8, C9, C10, C11, C12, C15, C20, C21, C22, C23, ...
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Item Qty. Reference Designator H1, H2 P21, P22 1 Parts not populated. Table 12. AD9445-125 IF Customer Evaluation Board Bill of Materials Item Qty. Reference Designator 1 ...
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AD9445 Item Qty. Reference Designator 29 23 C13, C14, C16, C17, C18, C19, C29, C31, C36, C37, C41, C45, C49, C61, C69, C70, C72, C73, C75, C93, 1 C108, C109, C110 C98 1 31 E15 1 32 ...
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OUTLINE DIMENSIONS 0° MIN 1.05 0.20 1.00 0.09 0.95 7° 3.5° 0.15 0° SEATING 0.05 0.08 MAX PLANE COPLANARITY VIEW A ROTATED 90 ° CCW NOTES 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2. THE PACKAGE HAS A CONDUCTIVE ...
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AD9445 NOTES Rev Page ...
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NOTES Rev Page AD9445 ...
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AD9445 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05489–0–10/05(0) Rev Page ...