CDB5451A Cirrus Logic Inc, CDB5451A Datasheet - Page 8

• Manufacturer Part Number: CDB5451A
• Description: EVAL BOARD CS5451A 6CH ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5451A

• Number Of Adc's: 6
• Number Of Bits: 6
• Data Interface: Serial
• Inputs Per Adc: 2 Differential
• Input Range: 1.6 Vpp
• Power (typ) @ Conditions: 27mW @ 3 V
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5451A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1009

FOUT,” the CS5451A’s on-chip reference provides
1.2 volts. With HDR14 set to position “LT1004,” the
LT1004 provides 1.23 volts (the LT1004 tempera-
ture drift is typically 50 ppm/°C). By setting
HDR14’s jumpers to position “EXT VREF,” the
user can supply an external voltage reference to
J16 connector post (VREF) and AGND inputs.
2.3.3 Clock Source for XIN
A 4.000 MHz crystal is provided to drive the XIN in-
put of the CS5451A. (See Figure 1.) However, the
user has the option to provide an external oscillator
signal for XIN, by switching the setting of HDR15.
2.3.4 S1 DIP Switch
Referring to Figure 3, the two single-pole single-
throw switches on SW1 DIP switch should be used
to control the logic settings on the CS5451A’s
OWRS pin and GAIN pin.
switches are set to “OPEN” the corresponding pin
on CS5451A is set to D+ potential, which creates a
logic-high state. When the user closes either of
these SW1 switches, the corresponding pin on
CS5451A is grounded, which creates a logic-low
state on the pin.
2.3.5 Reset Circuit
Circuitry has been provided which allows the user
to execute a hardware reset on the CS5451A.
(See Figure 3). By pressing on the S1 switch, the
RESET pin on the CS5451A will be held low until
the switch is released.
2.3.6 External Signal In/Out Header
Note that HDR16 is included on the CDB5451A
Evaluation Board as a header that is normally left
unconnected. This header provides a way for the
8
Reference
VREFOUT
EXTVREF
LT1004
Table 3. Reference Selection
Select reference sup-
plied from CS5451A
LT1004 Reference
Select on board
Select external
VREFOUT pin
Description
(5 ppm/
reference
°C)
When these SW1
O
O
O
O
O
O
O
O
O
HDR14
O
O
O
O
O
O
O
O
O
EXT VREF
VREFOUT
EXT VREF
VREFOUT
EXT VREF
VREFOUT
LT1004
LT1004
LT1004
user to interface the CDB5451A Evaluation Board
to other prototype boards, calibrators, logic analyz-
ers, other peripherals, etc. in order to further eval-
uate the CS5451A device and/or to use the
evaluation board as a platform for the prototype
development of a digital power meter solution.
However, please note that the CDB5451A Evalua-
tion Board is not intended to be integrated directly
into a commercial power meter. The layout of the
board is not optimized for practical power metering
situations.
2.3.7 Serial-to-Parallel Interface
Glue-logic on the evaluation board converts the
CS5451A serial data into 8-bit segments (bytes).
The bytes are sent to the DB25 connector (J17),
and then through the standard printer cable to the
user’s PC. This section briefly describes the oper-
ation of the digital circuitry on the CDB5451A that
provides the 8-bit parallel data to the PC. Refer to
Figure 3.
The user should recall from CS5451A Data Sheet
that the serial interface on the CS5451A device is
a “master-mode” interface, which means that the
device provides the clock. Once the CS5451A is
powered on, the SCLK pin produces a clock signal,
and data is sent out on the SDO pin of the device.
When the evaluation software is instructed (by the
user) to acquire data through the parallel interface,
a two-step process is performed: First the soft-
ware synchronizes itself to the frame rate of the
CS5451A, then the software acquires multiple
frames of data from the CS5451A.
2.3.7.1. Synchronization
When the software is commanded to acquire data,
the software will first synchronize itself to the frame
rate of the CS5451A (see CS5451A Data Sheet).
This is done by measuring the amount of time be-
tween rising and falling edges of the “BUSY” sig-
nal. (BUSY will change state every time the
CS5451A issues eight SCLKs--See next section
for a more detailed description.) By measuring this
time period, the software can determine the idle
period of the frame, which allows it to be prepared
to collect a complete frame’s worth of data when
the next CS5451A frame is received. This acquisi-
tion sequence is described next.
CDB5451A
DS458DB3