MAX1270EVKIT Maxim Integrated Products, MAX1270EVKIT Datasheet - Page 13

• Manufacturer Part Number: MAX1270EVKIT
• Description: EVALUATION KIT FOR MAX1270
• Manufacturer: Maxim Integrated Products

Specifications of MAX1270EVKIT

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 110k
• Data Interface: Serial
• Inputs Per Adc: 8 Single Ended
• Input Range: ±10 V
• Power (typ) @ Conditions: 30mW @ 110kSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1270, MAX1271, MAX127, MAX128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

In internal clock mode, the MAX1270/MAX1271 gener-
ate their conversion clock internally. This frees the
microprocessor from the burden of running the acquisi-
tion and the SAR conversion clock, and allows the con-
version results to be read back at the processor’s
convenience, at any clock rate from 0 to typically
10MHz.
SSTRB goes low after the falling edge of the last bit
(PD0) of the control byte has been shifted in, and
returns high when the conversion is complete.
Acquisition is completed and conversion begins on the
falling edge of the 4th internal clock pulse after the con-
trol byte; conversion ends on the falling edge of the
Figure 7. External Clock Mode—SSTRB Detailed Timing
Figure 8. External Clock Mode—18 Clocks/Conversion Timing
SSTRB
DOUT
SSTRB
A/D STATE
SCLK
CS
HIGH-Z
HIGH-Z
SCLK
CS
DIN
MSB
START SEL2 SEL1 SEL0
HIGH-Z
1
Internal Clock Mode (PD1 = 0, PD0 = 0)
CONTROL BYTE 0
______________________________________________________________________________________
RNG
BIP
PD1 PD0
LSB
18 SCLK
t
ACQUISITION
SDV
8
6 SCLK
13
MSB
D11 D10 D9
14
SCLK 12
Multirange, +5V, 8-Channel,
16
D8
CONVERSION
12 SCLK
D7
RESULT
START SEL2 SEL1 SEL0
D6
19
D5
16th internal clock pulse (12 internal clock cycle pulses
are used for conversion). SSTRB will remain low for a
maximum of 15µs, during which time SCLK should
remain low for best noise performance. An internal reg-
ister stores data while the conversion is in progress.
The MSB of the result byte (D11) is present at DOUT
starting at the falling edge of the last internal clock of
conversion. Successive falling edges of SCLK will shift
the remaining data out of this register (Figure 9).
Additional SCLK edges will result in zeros on DOUT.
go into a high-impedance state when CS goes high.
Pulling CS high prevents data from being clocked in
and tri-states DOUT, but does not adversely affect a
When internal clock mode is selected, SSTRB does not
CONTROL BYTE 1
D4
18 SCLK
D3
t
SSTRB
RNG
D2
D1 D0
BIP
24
Serial 12-Bit ADCs
PD1 PD0
LSB
26
ACQUISITION
6 SCLK
t
SSTRB
31
D11
32
D10
D9
CONVERSION
12 SCLK
RESULT 1
D8
CONTROL BYTE 2
D7
START SEL2
D6
HIGH-Z
37
D5
t
STR
13