IRDC3810 International Rectifier, IRDC3810 Datasheet - Page 13

• Manufacturer Part Number: IRDC3810
• Description: BOARD EVAL SYNC BUCK CONVERTER
• Manufacturer: International Rectifier

11/04/08
Feedback Compensation
The IR3810 is a voltage mode controller; the
control loop is a single voltage feedback path
including error amplifier and error comparator. To
achieve fast transient response and accurate
output regulation, a compensation circuit is
necessary. The goal of the compensation
network is to provide a closed loop transfer
function with the highest 0dB crossing frequency
and adequate phase margin (greater than 45
The output LC filter introduces a double pole, –
40dB/decade gain slope above its corner
resonant frequency, and a total phase lag of 180
(see figure 13). The resonant frequency of the LC
filter expressed as follows:
Figure 13 shows gain and phase of the LC filter.
Since we already have 180
output filter along, the system risks being
unstable.
The IR3810’s error amplifier is a differential-input
transconductance
available for DC gain control or AC phase
compensation.
The error amplifier can be compensated either in
type II or typeIII compensation. When it is used in
type II compensation the transconductance
properties of the error amplifier become evident
and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC
circuit from Comp pin to ground as shown in
figure 14.
This method requires that the output capacitor
should have enough ESR to satisfy stability
requirements. In general the output capacitor’s
ESR generates a zero typically at 5kHz to 50kHz
which is essential for an acceptable phase
margin.
0dB
Gain
F
Fig. 13: Gain and Phase of LC filter
LC
=
2
F
LC
π
Frequency
-40dB/decade
1
L
o
amplifier.
C
o
-180
-
- -
0
Phase
o
(11)
phase shift from the
The
F
LC
output
Frequency
o
).
is
o
The ESR zero of the output capacitor expressed
as follows:
The transfer function (Ve/Vo) is given by:
The (s) indicates that the transfer function varies
as a function of frequency. This configuration
introduces a gain and zero expressed by:
The gain is determined by the voltage divider and
error amplifier’s transconductance gain.
First select the desired zero-crossover frequency
(Fo):
Use the following equation to calculate R3:
Where:
V
V
F
F
F
R
g
m
o
ESR
LC
in
osc
8
= Crossover Frequency
and R
= Error Amplifier Transconductance
= Maximum Input Voltage
V
= Resonant Frequency of the Output Filter
( H
= Oscillator Ramp Voltage
OUT
= Zero Frequency of the Output Capacitor
H(s) dB
Fig. 14: TypeII compensation network
R
) s
R
R
8
9
[
F
=
3
9
H
F
V
z
=
= Feedback Resistor Dividers
o
( )
F
REF
=
Fb
Gain(dB)
and its asymptotic gain plot
s
g
V
>
ESR
2
m
]
osc
F
π
=
*
ESR
=
*
V
⎛
⎜ ⎜
⎝
R
*
F
in
2
g
R
9
1
and
o
*
R
m
∗
+
3
E/A
*
F
9
*
π
*
R
F
F
LC
R
C
2
ESR
*
8
Z
F
9
*
4
ESR
IR3810MPbF
o
R
1
+
R
( *
*
≤
9
Frequency
R
9
1
Comp
(
R
*
1/5
8
-
+
*
8
g
⎞
⎟ ⎟
⎠
- -
sC
sR
C
R
*
+
m
~
o
C
(15)
R
R
3
4
3
C
1/10
4
3
9
-
Ve
)
4
- -
-
- -
-
PD-60344
)
(12)
-
- -
*
- -
C
(14)
F
(13)
s
POLE
(16)
13