IRDC3831 International Rectifier, IRDC3831 Datasheet
IRDC3831
Related parts for IRDC3831
IRDC3831 Summary of contents
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SupIRBuck TM SYNCHRONOUS BUCK REGULATOR FOR DDR APPLICATIONS Features • Wide Input Voltage Range 1.0V to 16V • Wide Output Voltage Range 0.6V to 0.9*Vin • Continuous 8A Load Capability • Integrated Bootstrap-diode • High Bandwidth E/A for excellent transient ...
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ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND unless otherwise specified) • Vin ……………………………………………………. -0.3V to 25V • Vcc ……………….….…………….……..……….…… -0. (Note2) • Boot ……………………………………..……….…. -0.3V to 33V • SW …………………………………………..……… -0.3V to 25V(DC), -4V to 25V(AC, 100ns) • ...
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Block Diagram Fig. 2. Simplified block diagram of the IR3831 11/05/10 IR3831MPbF 3 ...
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Pin Description Pin Name Track pin. Use External resistors from VDDQ rail. The Vp voltage can set to 0.9V for DDR2 application and 0.75 or 0.6V for DDR3 application. Inverting input to the error amplifier. This pin ...
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Recommended Operating Conditions Symbol Definition V Input Voltage in V Supply Voltage cc Boot to SW Supply Voltage V Output Voltage o I Output Current o Fs Switching Frequency T Junction Temperature j Electrical Specifications Unless otherwise specified, these specification ...
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Electrical Specifications (continued) Unless otherwise specified, these specification apply over 4.5V< C<T < 125 C. Typical values are specified Parameter Symbol Oscillator Rt Voltage Frequency F S Ramp Amplitude Vramp Ramp Offset Ramp ...
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Electrical Specifications (continued) Unless otherwise specified, these specification apply over 4.5V< C<T < 125 C. Typical values are specified Parameter SYM Thermal Shutdown Thermal Shutdown Note4 Hysteresis Note4 Power Good Power Good upper ...
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TYPICAL OPERATING CHARACTERISTICS (-40 Icc(Stan db y) 240.0 220.0 200.0 180.0 -40 - 701.0 700.5 700.0 699.5 699.0 698.5 698.0 697.5 697.0 696.5 696.0 -40 -20 0 ...
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Typical Efficiency and Power Loss Curves Vin=12V, Vo=0.75V, Io=1A- 8A, Vcc=5V, Fs=400kHz Room Temperature, No Air Flow 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 ...
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Typical Efficiency and Power Loss Curves Vin=5V, Vo=0.75V, Io=1A- 8A, Vcc=5V, Fs=400kHz Room Temperature, No Air Flow 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 11/05/10 3 ...
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Circuit Description THEORY OF OPERATION Introduction The IR3831 uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency is programmable from 250kHz ...
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Figure 3c. shows the recommended startup sequence for tracking operation of IR3831 with Enable used as logic input. Fig. 3c. Recommended startup sequence, Sequenced operation Pre-Bias Startup IR3831 is able to start up into pre-charged output, which prevents oscillation disturbances ...
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Operating Frequency The switching frequency can be programmed between 250kHz – 1500kHz by connecting an external resistor from R pin to Gnd. Table 1 t tabulates the oscillator frequency versus R Table 1. Switching Frequency and I External Resistor (R ...
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Thermal Shutdown Temperature sensing is provided inside IR3831. The trip threshold is typically set to 140 trip threshold is exceeded, thermal shutdown turns off both MOSFETs and discharges the soft start capacitor. Automatic restart is initiated when the sensed temperature ...
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Minimum on time Considerations The minimum ON time is the shortest amount of time for which the Control FET may be reliably turned on, and this depends on the internal timing delays. For the IR3831, the typical minimum on-time is ...
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Application Information Design Example: The following example is a typical application for IR3831. The application circuit is shown on page 22 13.2V max 0. ≤ ...
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Bootstrap Capacitor Selection To drive the Control FET necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin, which is connected the source of the Control FET . This is achieved ...
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Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors type and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the : actual capacitance value and the Equivalent Series ...
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V Z OUT E REF Gain(dB) H( Fig. 13. Type II compensation network and its asymptotic gain plot The transfer function ( given by: e ...
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V OUT E REF Gain(dB) H( Fig.14. Type III Compensation network and its asymptotic gain plot The ...
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Detailed calculation of compensation TypeIII o Θ = Desired Phase Margin 70 − Θ sin 10.58 kHz Θ sin 1 + Θ sin 340.28 kHz P ...
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... NPO, 5% Panasonic- ECG 0603, 50V, X7R, 10% Panasonic - ECG Thick Film, 0603,1/10W,1% Rohm Thick Film, 0603,1/10W,1% Panasonic - ECG 0603, 50V, X7R, 10% Panasonic - ECG SupIRBuck PQFN 5x6mm International Rectifier IR3831MPbF Part Number EEV-FK1E331P ECJ-3YX1C106K MPL104-0R6 ECJ-2FB0J226ML MCR03EZPFX4991 MCR03EZPFX7500 MCR03EZPFX3572 MCR03EZPFX4021 MCR03EZPFX4701 ...
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TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=5V, Vo=0.75V, Io=0- ±8A, Room Temperature, No Air Flow Fig. 16: Start up at 8A, sourcing current out 2 DDQ Ch :SS, Ch :PGood 3 4 Fig. 18: Inductor node ...
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TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=0.75V, Room Temperature, No Air Flow Fig. 22: Tracking 8A, sourcing current out 3 DDQ Ch :PGood 4 Fig. 24: Transient Response, 1A/us -0.5A to +0.5A load , ...
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TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=0.75V, Io=+8A, Room Temperature, No Air Flow Fig.25: Bode Plot at 8A load (sourcing current) shows a bandwidth of 43kHz and phase margin of 11/05/10 IR3831MPbF 63 degrees 25 ...
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Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make all the connections for components in the top ...
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Feedback trace should be kept away form noise sources Fig. 26b. IR3831 layout considerations – Bottom Layer Analog Ground plane Single point connection between AGND & PGND, should be close to the SupIRBuck, kept away from noise sources. Fig. 26c. ...
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PCB Metal and Components Placement Lead lands (the 11 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to ...
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Solder Resist It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should ...
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Stencil Design • The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited ...
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IR WORLD HEADQUARTERS: This product has been designed and qualified for the Consumer market 11/05/10 BOTTOM VIEW 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Visit us at www.irf.com for sales contact information Data and specifications subject ...