MAX5080EVKIT Maxim Integrated Products, MAX5080EVKIT Datasheet - Page 13

• Manufacturer Part Number: MAX5080EVKIT
• Description: EVAL KIT FOR MAX5080
• Manufacturer: Maxim Integrated Products

Specifications of MAX5080EVKIT

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 3.3V
• Current - Output: 1A
• Voltage - Input: 4.5 ~ 40V
• Regulator Topology: Buck
• Frequency - Switching: 250kHz
• Board Type: Fully Populated
• Utilized Ic / Part: MAX5080
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

equal to 20% and 80%, respectively. ∆I
peak inductor current (see the Input Capacitors Selection
section) and f
The allowable deviation of the output voltage during
fast load transients also determines the output capaci-
tance, its ESR, and its equivalent series inductance
(ESL). The output capacitor supplies the load current
during a load step until the controller responds with a
greater duty cycle. The response time (t
depends on the closed-loop bandwidth of the converter
(see the Compensation Design section). The resistive
drop across the output capacitors ESR, the drop
across the capacitors ESL (∆V
discharge causes a voltage droop during the load-
step. Use a combination of low-ESR tantalum/aluminum
electrolyte and ceramic capacitors for better transient
load and voltage ripple performance. Nonleaded
capacitors and capacitors in parallel help reduce the
ESL. Keep the maximum output voltage deviation
below the tolerable limits of the electronics being pow-
ered. Use the following equations to calculate the
required ESR, ESL, and capacitance value during a
load step:
where I
load step, and t
controller.
The MAX5080/MAX5081 use a voltage-mode control
scheme that regulates the output voltage by comparing
the error amplifier output (COMP) with an internal ramp
to produce the required duty cycle. The output lowpass
LC filter creates a double pole at the resonant frequen-
cy, which has a gain drop of -40dB/decade. The error
amplifier must compensate for this gain drop and phase
shift to achieve a stable closed-loop system.
The basic regulator loop consists of a power modulator,
an output feedback divider, and a voltage error amplifi-
er. The power modulator has a DC gain set by
V
the output inductance (L), the output capacitance
IN
/V
RAMP
STEP
, with a double pole and a single zero set by
is the load step, t
SW
C
E
OUT
E
is the converter’s switching frequency.
SR
RESPONSE
SL
______________________________________________________________________________________
=
=
=
∆
I
∆
I
STEP
STEP
V
V
ESR
ESL
I
STEP
Compensation Design
is the response time of the
×
×
∆
t
STEP
RESPONSE
V
t
STEP
ESL)
Q
is the rise time of the
, and the capacitor
P-P
1A, 40V, MAXPower Step-Down
is the peak-to-
RESPONSE
)
(C
equivalent series resistance (ESR). The power modula-
tor incorporates a voltage feed-forward feature, which
automatically adjusts for variations in the input voltage
resulting in a DC gain of 10. The following equations
define the power modulator:
The switching frequency is internally set at 250kHz or
can vary from 150kHz to 350kHz when driven with an
external SYNC signal. The crossover frequency (f
which is the frequency when the closed-loop gain is
equal to unity, should be set at 15kHz or below therefore:
The error amplifier must provide a gain and phase
bump to compensate for the rapid gain and phase loss
from the LC double pole. This is accomplished by utiliz-
ing a type 3 compensator that introduces two zeroes
and 3 poles into the control loop. The error amplifier
has a low-frequency pole (f
The two zeros are at:
and the higher frequency poles are at:
Figure 3 shows the error amplifier feedback as well as
its gain response for circuits that use low-ESR output
capacitors (ceramic). In this case f
f
pensate for the gain and phase loss due to the double
pole. Choose the inductor (L) and output capacitor
(C
Capacitor Selection section.
Z1
f
P
OUT
2
OUT
f
is set to 0.8 x f
Z1
=
) (C5 in the Typical Application Circuit) and its
=
2
) as described in the Inductor and Output
π
2
π
×
DC-DC Converters
×
R
1
f
LC
R
6
1
G
f
5
ZESR
×
MOD DC
=
×
C
LC(MOD)
C
2
6
π
7
(
=
and f
Compensation When f
f
and
L
C
2
)
×
π
≤15kHz
1
=
C
P
×
P1
f
and f
Z2
3
OUT
V
C
) near the origin.
RAMP
=
V
OUT
=
IN
1
2
Z2
2
π
π
ZESR
is set to f
×
×
×
=
ESR
R
(
10
R
5
6
occurs after f
×
+
1
1
⎛
⎜
⎝
R
C
C
LC
3
C
7
7
)
×
×
+
< f
to com-
C
C
C
ZESR
6
8
8
⎞
⎟
⎠
C
13
C
),
.