STM8/128-EVAL STMicroelectronics, STM8/128-EVAL Datasheet - Page 32

• Manufacturer Part Number: STM8/128-EVAL
• Description: BOARD EVAL FOR STM8S
• Manufacturer: STMicroelectronics
• Type: MCUr

Specifications of STM8/128-EVAL

• Mfg Application Notes: STM8S Getting Started
• Contents: Evaluation Board
• Silicon Manufacturer: ST Micro
• Core Architecture: STM8
• Core Sub-architecture: STM8
• Silicon Core Number: STM8
• Silicon Family Name: STM8S2xx
• Kit Contents: Board
• For Use With/related Products: STM8S2xx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8506

Pinouts and pin description
Table 6.
1. The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader. These pins are pulled up as
2. The beCAN interface is available on STM8S208xx devices only
3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to V
4. The PD1 pin is in input pull-up during the reset phase and after the internal reset release.
5. Available in 44-pin package only. On other packages, the AFR4 bit is reserved and must be kept at 0.
32/105
65 51
66 52
67 53 37
68 54 38 34
69 55 39 35
70 56 40 36
71
72
73 57 41 37 25 PD0/TIM3_CH2
74 58 42 38 26 PD1/SWIM
75 59 43 39 27 PD2/TIM3_CH1
76 60 44 40 28 PD3/TIM2_CH2
77 61 45 41 29
78 62 46 42 30 PD5/ UART3_TX
79 63 47 43 31
80 64 48 44 32 PD7/TLI
part of the bootloader activation process and returned to the floating state before a return from the bootloader.
not implemented).
Pin number
-
-
-
-
-
-
Pin description (continued)
-
-
-
-
-
- PG7
- PE4
- PE3/TIM1_BKIN
- PE2/I
- PE1/I
- PE0/CLK_CCO
- PI6
- PI7
PD4/TIM2_CH1/B
EEP
PD6/
UART3_RX
Pin name
2
2
C_SDA
C_SCL
(4)
(1)
I/O X
I/O X
I/O X
I/O X
I/O X
I/O X
I/O X
I/O X
I/O X
I/O X
I/O X
I/O X
I/O X
I/O X
I/O X
I/O X
Doc ID 14733 Rev 11
Input
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X HS O3 X
X HS O3 X
X HS O4 X
X HS O3 X
X HS O3 X
X HS O3 X
X
X
X
Output
O1 X
O1 X
O1 X
O1 T
O1 T
O1 X
O1 X
O1 X
O1 X
O1 X
(3)
(3)
X Port G7
X Port E4
X Port E3
X Port E0
X
X
X Port D0
X Port D1
X Port D2
X Port D3
X Port D4
X Port D5
X Port D6
X Port D7
Port E2 I
Port E1 I
Port I6
Port I7
STM8S207xx, STM8S208xx
Timer 1 -
break input
Configurable
clock output
Timer 3 -
channel 2
SWIM data
interface
Timer 3 -
channel 1
Timer 2 -
channel 2
Timer 2 -
channel 1
UART3 data
transmit
UART3 data
receive
Top level
interrupt
2
2
C data
C clock
alternate
function
Default
TIM1_BKIN
[AFR3]/
CLK_CCO
[AFR2]
TIM2_CH3
[AFR1]
ADC_ETR
[AFR0]
BEEP output
[AFR7]
TIM1_CH4
[AFR4]
after remap
[option bit]
Alternate
function
DD
are
(5)