C8051F005-TB Silicon Laboratories Inc, C8051F005-TB Datasheet - Page 113

• Manufacturer Part Number: C8051F005-TB
• Description: BOARD PROTOTYPING W/C8051F005
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005-TB

• Contents: Board
• Data Bus Width: 8 bit
• Silicon Manufacturer: Silicon Laboratories
• Core Architecture: 8051
• Silicon Family Name: C8051F00x
• Kit Contents: Board
• Features: JTAG Connector, Debug Adapter Interface, Analog I/O Configuration
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F005
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16. SMBus / I2C Bus
The SMBus serial I/O interface is compliant with the System Management Bus Specification, version 1.1. It is a
two-wire, bi-directional serial bus, which is also compatible with the I
interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial
transfer of the data. Data can be transferred at up to 1/8
allowed by the SMBus specification, depending on the system clock used). A method of extending the clock-low
duration is used to accommodate devices with different speed capabilities on the same bus.
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver, and
data transfers from an addressed slave transmitter to a master receiver. The master device initiates both types of
data transfers and provides the serial clock pulses. The SMBus interface may operate as a master or a slave.
Multiple master devices on the same bus are also supported. If two or more masters attempt to initiate a data
transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitration.
113
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
SMBUS
IRQ
S
V
L
6
S
L
V
5
SMB0ADR
S
L
V
4
B
U
S
Y
Interrupt
Request
B
S
V
L
3
E
N
S
M
B
S
V
7
L
2
SMB0CN
S
A
T
A
S
L
V
1
O
S
T
S
L
V
0
S
I
G
C
A
A
E
F
T
B
O
T
E
SFR Bus
0000000b
SMBUS CONTROL LOGIC
Arbitration
SCL Synchronization
Status Generation
SCL Generation (Master Mode)
IRQ Generation
A
7 MSBs
S
T
A
7
SFR Bus
S
T
A
6
Figure 16.1. SMBus Block Diagram
SMB0STA
S
T
A
5
S
T
A
4
8
S
T
A
3
SMB0DAT
S
A
T
2
Read
S
T
A
1
7
S
T
A
0
8
6
SMB0DAT
5
4
C
R
7
3
C
R
6
Clock Divide
Data Path
8
Control
2
SMB0CR
Rev. 1.7
C
R
5
Logic
1
SMB0DAT
C
R
4
Write to
0
C
R
3
C
R
2
th
C
R
1
of the system clock if desired (this can be faster than
Control
C
R
0
SDA
Control
SCL
1
0
SYSCLK
2
FILTER
FILTER
C serial bus. Reads and writes to the
N
N
SDA
SCL
C
R
O
S
S
B
A
R
Port I/O