SW006010 Microchip Technology, SW006010 Datasheet - Page 118

• Manufacturer Part Number: SW006010
• Description: MPLAB 17C SOFTWARE
• Manufacturer: Microchip Technology

Specifications of SW006010

• Tool Function: Compiler
• Tool Type: Compiler
• Processor Series: PIC17C
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: MPLAB®
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MPLAB
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C17 C Compiler Libraries
A function or variable has internal linkage if it can not be accessed from outside the
module in which it is defined.
International Organization for Standardization
An organization that sets standards in many businesses and technologies, including
computing and communications.
Interrupt
An asynchronous event that suspends normal processing and temporarily diverts the
flow of control through an "interrupt handler" routine.
Interrupts may be caused by both hardware (I/O, timer, machine check) and software
(supervisor, system call or trap instruction).
In general the computer responds to an interrupt by storing the information about the
current state of the running program; storing information to identify the source of the
interrupt; and invoking a first-level interrupt handler. This is usually a kernel level
privileged process that can discover the precise cause of the interrupt (e.g. if several
devices share one interrupt) and what must be done to keep operating system tables
(such as the process table) updated. This first-level handler may then call another
handler, e.g. one associated with the particular device which generated the interrupt.
Interrupt Handler
A routine which is executed when an interrupt occurs. Interrupt handlers typically deal
with low-level events in the hardware of a computer system such as a character arriving
at a serial port or a tick of a real-time clock. Special case is required when writing an
interrupt handler to ensure that either the interrupt which triggered the handler's
execution is masked out (inhibited) until the handler is done, or the handler is written in
a re-entrant fashion so that multiple concurrent invocations will not interfere with each
other.
If interrupts are masked then the handler must execute as quickly as possible so that
important events are not missed. This is often arranged by splitting the processing
associated with the event into "upper" and "lower" halves. The lower part is the interrupt
handler which masks out further interrupts as required, checks that the appropriate
event has occurred (this may be necessary if several events share the same interrupt),
services the interrupt, e.g. by reading a character from a UART and writing it to a
queue, and re-enabling interrupts.
The upper half executes as part of a user process. It waits until the interrupt handler
has run. Normally the operating system is responsible for reactivating a process which
is waiting for some low-level event. It detects this by a shared flag or by inspecting a
shared queue or by some other synchronization mechanism. It is important that the
upper and lower halves do not interfere if an interrupt occurs during the execution of
upper half code. This is usually ensured by disabling interrupts during critical sections
of code such as removing a character from a queue.
Interrupt Request
The name of an input found on many processors which causes the processor to
suspend normal instruction execution temporarily and to start executing an interrupt
handler routine. Such an input may be either "level sensitive" - the interrupt condition
will persist as long as the input is active or "edge triggered" - an interrupt is signaled by
a low-to-high or high-to-low transition on the input. Some processors have several
interrupt request inputs allowing different priority interrupts.
 2002 Microchip Technology Inc.