ATDM2170HP Atmel, ATDM2170HP Datasheet - Page 2

• Manufacturer Part Number: ATDM2170HP
• Description: CADENCE VERILOG LIB/INTRFC MAINT
• Manufacturer: Atmel
• Type: HP UX Basedr

Specifications of ATDM2170HP

• For Use With/related Products: AT6000 FPGA Development System
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AT6000 FPGA System Summary
The following is a summary of Integrated Development
System software, hardware, and annual maintenance
agreements. Detailed technical information is contained in
the individual product data sheets.
Atmel offers specially-priced University systems for se-
lected PC and Sun packages.
FPGA Physical Design System
(ATDS2100PC/ATDS2100SN)
The AT6000 Physical Design System includes the Atmel
Design Manager with PLD interface and macro libraries
for Viewlogic schematic capture synthesis and functional
simulation. Tools are included for macro generation, inter-
active editing, design rule checking, automatic placement
and routing, timing analysis, bitstream generation, and
PROM file generation.
Base PC and Sun system requirements for the Physical
Design System are listed on the next page.
Physical Design System/Viewlogic Standalone
Packages.
Several AT6000 Series design tool packages combine the
Physical Design System with Viewlogic schematic capture
and functional simulation options.
PC-based packages
Viewlogic’s PRO series for the PC includes PROcapture
(schematic entry), PROsim (gate simulation), and PRO-
synthesis (text-based entry).
Atmel offers the following PRO series packages:
Customers with Viewlogic restricted licenses may pur-
chase an Atmel 10K or 20K AT6000 Series Design Sys-
tem & Viewlogic restricted license upgrade.
A University system without a prototype kit is available for
the ATDS2100PC and ATDS2110PC.
4-26
ATDS2101PC. AT6000 Series Physical Design Sys-
tem with PROcapture Schematic Entry
ATDS2110PC. AT6000 Series Physical Design Sys-
tem with PROcapture and PROSim Gate Simulation
(10K gates)
ATDS2120PC. AT6000 Series Physical Design Sys-
tem with PROcapture and PROSim Gate Simulation
(20K gates)
ATDS2130PC.
VDHL Libraries & Interface for AT6000 Series Design
System
FPGA Overview
Viewlogic PROsynthesis, PROsim-
Sun-based packages
Viewlogic’s design tool family for Sun workstations is
called Powerview, and the schematic entry, gate simula-
tion, and text-based entry options are called ViewDraw,
ViewSim, and ViewSynthesis.
Atmel offers the following Powerview packages:
A University system is available for the ATDS2120SN.
Library and Interface packages
Atmel offers several library and interface packages for
customers who wish to use the AT6000 Series Physical
Design System with third-party software from other com-
panies:
PC-based library/interface package
ATDS2140PC. Exemplar Library & Interface for AT6000
Series Design System
Sun-based library/interface packages
ATDS2140SN. Exemplar Library & Interface for AT6000
Series Design System
ATDS2150SN. Mentor Library & Interface for AT6000 Se-
ries Design System
ATDS2160SN. Synopsys Library & Interface for AT6000
Series Design System
ATDS2170SN. Cadence Verilog/Concept Library & Inter-
face for AT6000 Series Design System
Annual Maintenance Agreements
Annual Maintenance Agreements are available for each
package and option in the Integrated Development Sys-
tem. The first year of maintenance is included in the pur-
chase price; renewal is optional. Maintenance Agree-
ments give users direct access to Atmel’s experienced
technical support staff and cover software upgrades that
keep engineers on the leading edge of Atmel’s design
tools. See the individual product data sheets for ordering
and pricing information.
Extended maintenance agreements are not available for
University systems.
ATDS2120SN. AT6000 Physical Design System with
Powerview Schematic Entry and Viewlogic Simulator
(20K gates)
ATDS2130SN.
VDHL Libraries & Interface for AT6000 Series Design
System
Viewlogic Viewsynthesis, ViewSim-