89C5121-SK1 Atmel, 89C5121-SK1 Datasheet - Page 93

• Manufacturer Part Number: 89C5121-SK1
• Description: KIT SMART CARD FOR AT89C5121
• Manufacturer: Atmel
• Type: Smart Cardr

Specifications of 89C5121-SK1

• Contents: Board
• For Use With/related Products: AT89C5121
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: T89C5121-SK1; T89C5121-SK1

Table 67. SCON Register
SCON (S:98h)
Serial Control Registe
Reset Value = XXX0 0000b
4164G–SCR–07/06
Number
FE/SM0
Bit
7
6
5
4
3
2
1
0
7
Mnemonic
SM0
SM1
SM2
REN
RB8
TB8
Bit
FE
TI
RI
SM1
6
Description
Framing Error bit
To select this function, set SMOD0 bit in PCON register.
Set by hardware to indicate an invalid stop bit.
Must be cleared by software.
Serial Port Mode bit 0
To select this function, clear SMOD0 bit in PCON register.
Software writes to bits SM0 and SM1 to select the Serial Port operating mode.
Refer to SM1 bit for the mode selections.
Serial Port Mode bit 1
To select this function, set SMOD0 bit in PCON register.
Software writes to bits SM1 and SM0 to select the Serial Port operating mode.
SM0
0
0
1
1
Serial Port Mode bit 2
Software writes to bit SM2 to enable and disable the multiprocessor communication and automatic address
recognition features.
This allows the Serial Port to differentiate between data and command frames and to recognize slave and broadcast
addresses.
Receiver Enable bit
Clear to disable reception in mode 1, 2 and 3, and to enable transmission in mode 0.
Set to enable reception in all modes.
Transmit bit 8
Modes 0 and 1: Not used.
Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8.
Receiver bit 8
Mode 0: Not used.
Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit received.
Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit received.
Transmit Interrupt flag
Set by the transmitter after the last data bit is transmitted.
Must be cleared by software.
Receive Interrupt flag
Set by the receiver after the stop bit of a frame has been received.
Must be cleared by software.
SM2
SM1
5
0
1
0
1
Mode Description
0
1
2
3
Shift Register
8-bit UART
9-bit UART
9-bit UART
REN
4
Baud Rate
F
Variable
F
Variable
OSC
OSC
/12 or variable if SRC bit in BDRCON is set
/32 or F
TB8
3
OSC
/64
RB8
2
TI
1
A/T8xC5121
RI
0
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