AD15700/PCB Analog Devices Inc, AD15700/PCB Datasheet
AD15700/PCB
Specifications of AD15700/PCB
Related parts for AD15700/PCB
AD15700/PCB Summary of contents
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FEATURES 16-Bit A/D Converter 1 MSPS S/( Typ @ 250 kHz No Pipeline Delay 14-Bit D/A Converter Settling Time S/ Typ 2 80 MHz Amplifiers Slew Rate Rail-to-Rail Input ...
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AD15700–SPECIFICATIONS 16-BIT ADC ELECTRICAL CHARACTERISTICS Parameter RESOLUTION ANALOG INPUT Voltage Range Common-Mode Input Voltage Analog Input CMRR Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate Time between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity ...
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Parameter DIGITAL OUTPUTS Data Format Pipeline Delay POWER SUPPLIES Specified Performance AVDD DVDD OVDD 4 Operating Current AVDD 5 DVDD 5 OVDD 5, 6 Power Dissipation 8 In Power-Down Mode TEMPERATURE RANGE Specified Performance NOTES LSB ...
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AD15700 16-BIT ADC TIMING CHARACTERISTICS Parameter Refer to Figures 14 and 15 Convert Pulsewidth Time between Conversions (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except in Master Serial Read after Convert Mode (Warp ...
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Table II. Serial Clock Timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum ...
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AD15700 14-BIT DAC ELECTRICAL CHARACTERISTICS Parameter STATIC PERFORMANCE Resolution Relative Accuracy, INL Differential Nonlinearity Gain Error Gain Error Temperature Coefficient Zero Code Error Zero Code Temperature Coefficient OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Digital-to-Analog Glitch Impulse Digital ...
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DAC TIMING CHARACTERISTICS Parameter Limit MIN MAX f 25 SCLK ...
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AD15700 AMPLIFIER ELECTRICAL CHARACTERISTICS Parameter DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth Slew Rate Settling Time to 0.1% DISTORTION/NOISE PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Differential Phase DC PERFORMANCE Input Offset Voltage Offset Drift ...
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AMPLIFIER ELECTRICAL CHARACTERISTICS Parameter DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth Slew Rate Settling Time to 0.1% DISTORTION/NOISE PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Differential Phase DC PERFORMANCE Input Offset Voltage Offset Drift Input ...
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... ADDS-2191-EZLITE ADDS-21535-EZLITE ADDS-21160M-EZLITE ADDS-21161N-EZLITE *One of the DSP Evaluation Kits is required for operation of the AD15700/PCB Evaluation Board. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD15700 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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ADC PIN FUNCTION DESCRIPTIONS (See Pinout, page 42) Pin No. Mnemonic Type H9, J8, AGND_ADC P J9, M12 M6 AVDD P L7 BYTESWAP DI L8 OB/ WARP DI L9 IMPULSE DI M8 SER/PAR DI M9, L10 D[0:1] DO ...
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AD15700 ADC PIN FUNCTION DESCRIPTIONS (continued) Pin No. Mnemonic Type H10 DGND_ADC P H12 D[8] or SDOUT DO H11 D[9] or SCLK DI/O G12 D[10] or SYNC DO G11 D[11] or RDERROR DO F12, F11, D[12:15] DO E12, E11 G10 ...
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Pin No. Mnemonic A6 VOUT_DAC A3, C3, C4 AGND_DAC A2 VREF CS_DAC B1 E1 SCLK E2 DIN E3 DGND_DAC C6 VDD_DAC Pin No. Mnemonic C9 (J1) +IN1(2) A9 (G1) –IN1(2) B12 (K4) VOUT1(2) A11 (F3) +VS1(2) B10, B11 –VS1(2) (G3, ...
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AD15700 ADC DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as negative full scale occurs 1/2 ...
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D/A CONVERTER 2.5 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 –2.5 0 16384 32768 CODE TPC 1. Integral Nonlinearity vs. Code 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0.00 –0.25 –0.50 –0.75 –1.00 0 16384 32768 CODE ...
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AD15700 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 0 100 200 300 FREQUENCY – kHz TPC 7. FFT Plot 100 95 SNR 90 SINAD 100 FREQUENCY – kHz TPC 8. SNR, ...
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C – TPC 13. Typical Delay vs. Load Capacitance C 100000 AVDD, WARP/NORMAL 10000 DVDD, WARP/NORMAL 1000 100 AVDD, IMPULSE 10 DVDD, IMPULSE 0 0.1 OVDD, ALL MODES 0.01 ...
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AD15700 14-BIT D/A CONVERTER 0.50 0.25 0 –0.25 –0.50 2048 0 4096 6144 8192 10240 CODE – Decimal TPC 16. Integral Nonlinearity vs. Code 0.50 0.25 0 –0.25 –0.50 –60 – TEMPERATURE – C TPC 17. Integral Nonlinearity ...
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TEMPERATURE – C TPC 22. Gain Error vs. Temperature 250 LOGIC V = 2.5V REF 200 150 –40 –20 ...
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AD15700 –5 –4 –3 –2 – – TPC 28. Typical V Distribution @ V OS 2.5 2 ...
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AMPLIFIER 2.7V CC –0 –1.0 –1 10V CC –2.0 –2.5 100 1k R – LOAD TPC 34. +Output Saturation Voltage vs 2.7V CC –0 ...
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AD15700 110 105 100 – – LOAD TPC 40. Open-Loop Gain ( – –40 –30 ...
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FREQUENCY – MHz TPC 46. Unity Gain, –3 dB Bandwidth –16dBm IN + –1 –2 V ...
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AD15700 65V 2. 10k 100k FUNDAMENTAL FREQUENCY – Hz TPC 52. Large Signal Response 100 0.1 ...
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GND s/DIV TPC 58. Output Swing 3.1 2.9 2.7 2.5 2.3 2.1 1.9 50ns/DIV TPC 59 Step Response REV. A 2.85 2.35 1.85 1.35 0.85 0. ...
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AD15700 CIRCUIT OPERATION The AD15700 contains precision components for interfacing analog I processor. Configuration for particular applications can be made with short external interconnects under the device. ANALOG INPUT (0.2V TO 2REF) ADR421 OR AD780 2.5V OR 3.0V ...
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Analog Input Section Made buffer amplifier filter, and an ADC, the analog input circuit allows measurement of voltages ranging from 0 REF V. When placed in the REF input ...
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AD15700 4R IND REF 4R REFGND INC 2R INB 32768C R INA INGND By switching each element of the capacitor array between REFGND or REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4. . .VREF/65536). The control ...
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Analog Inputs The ADC is specified to operate with six full-scale analog input ranges. Connections required for each of the four analog inputs, IND, INC, INB, INA, and the resulting full-scale ranges are shown in Table I. The typical input ...
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AD15700 Driver Amplifier Choice Although the ADC is easy to drive, the driver amplifier needs to meet at least the following requirements: ∑ The driver amplifier and the ADC analog input circuit must be able, together, to settle for a ...
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WARP/NORMAL 10000 1000 100 10 IMPULSE 1 0 100 1000 SAMPLING RATE – SPS Figure 13. Power Dissipation vs. Sample Rate CONVERSION CONTROL Figure 14 shows the detailed timing diagrams of the conversion process. The ADC is ...
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AD15700 PARALLEL INTERFACE The ADC is configured to use the parallel interface when the SER/PAR is held low. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as ...
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CS_ADC CNVST BUSY SYNC t 14 SCLK t 15 SDOUT t Figure 20. Master Serial Data Timing for Reading (Read after Convert) CS_ADC, RD CNVST BUSY SYNC SCLK SDOUT t 16 Figure 21. ...
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AD15700 While the ADC is performing a bit decision important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is particu- larly important during the second half of the ...
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MICROPROCESSOR INTERFACING The ADC is ideally suited for traditional dc measurement appli- cations supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. The ADC is designed to interface either with a parallel 8-bit or 16-bit ...
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AD15700 The AD15700’s ADC has five different ground pins: INGND, REFGND, AGND, DGND, and OGND. INGND is used to sense the analog input signal. REFGND senses the reference voltage and should be a low impedance return to the reference because ...
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Serial Interface The DAC is controlled by a versatile 3-wire serial interface that operates at clock rates MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. The timing diagram can be seen in Figure ...
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AD15700 ADSP-2101/ADSP-2103 to DAC Interface Figure 33 shows a serial interface between the DAC and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set to operate in the SPORT (Serial Port) Transmit Alternate Framing Mode. The ADSP-2101/ADSP-2103 is programmed through the SPORT ...
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Decoding Multiple DACs The CS_DAC pin of the DAC can be used to select one of a number of DACs. All devices receive the same serial clock and serial data, but only one device will receive the CS_DAC signal at ...
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AD15700 Overdriving the Input Stage Sustained input differential voltages greater than 3.4 V should be avoided as the input transistors may be damaged. Input clamp diodes are recommended if the possibility of this condition exists. The voltages at the collectors ...
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High Performance Single-Supply Line Driver Even though the amplifier swings close to both rails, the amplifier has optimum distortion performance when the signal has a common- mode level halfway between the supplies and when there is about 500 mV of ...
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AD15700 AGND A COMMON VREF DAC CS_DAC B COMMON COMMON AGND C COMMON COMMON DAC D COMMON COMMON COMMON DGND SCLK E DIN DAC F COMMON COMMON +VS2 G –IN2 COMMON –VS2 H COMMON COMMON –VS2 J ...
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A1 1.70 MAX REV. A OUTLINE DIMENSIONS 144-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-144) Dimensions shown in millimeters 10.00 BSC TOP VIEW DETAIL A 0.25 MIN ...
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AD15700 Revision History Location 2/03—Data Sheet changed from REV REV. A. Edit to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . ...