AD9763-EB Analog Devices Inc, AD9763-EB Datasheet
AD9763-EB
Specifications of AD9763-EB
Related parts for AD9763-EB
AD9763-EB Summary of contents
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... Each DAC provides differential current output, thus supporting single-ended or dif- ferential applications. Both DACs of the AD9763, AD9765, or AD9767 can be simultaneously updated and can provide a nominal full-scale current of 20 mA. The full-scale currents between each DAC are matched to within 0 ...
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... Analog Outputs .......................................................................... 23 Digital Inputs .............................................................................. 24 DAC Timing ................................................................................ 24 Sleep Mode Operation ............................................................... 26 Power Dissipation....................................................................... 26 Applying the AD9763/AD9765/AD9767 .................................... 28 Output Configurations .............................................................. 28 Differential Coupling Using a Transformer ............................ 28 Differential Coupling Using an Op Amp ................................ 28 Single-Ended, Unbuffered Voltage Output ............................. 29 Single-Ended, Buffered Voltage Output Configuration ........ 29 ...
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... Changes to Figure 29 ...................................................................... 21 2/00—Rev Rev. B 12/99—Rev Rev. A AD9763/AD9765/AD9767 Revision History: AD9765 1/08—Rev Rev. E Combined with AD9763 and AD9767 Data Sheets ...... Universal Changes to Figure 1 .......................................................................... 1 Changes to Applications Section ..................................................... 1 Changes to Timing Diagram Section ............................................. 7 Change to Absolute Maximum Ratings ......................................... 8 Added Figure 3 and Figure 5 ........................................................... 9 Changes to Table 6 ...
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... AD9763/AD9765/AD9767 Revision History: AD9767 1/08—Rev Rev. E Combined with AD9763 and AD9765 Data Sheets ....... Universal Changes to Figure 1 .......................................................................... 1 Changes to Features Section............................................................ 1 Changes to Applications Section .................................................... 1 Changes to Timing Diagram Section ............................................. 7 Change to Absolute Maximum Ratings ......................................... 8 Added Figure 3 and Figure 4 ........................................................... 9 Changes to Table 6 .......................................................................... 10 Added Figure 6 to Figure 39 .......................................................... 11 Added Note to Figure 58 ...
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... REF = 20 mA and Ω and LOAD OUTA OUTB CLK Rev Page AD9763/AD9765/AD9767 AD9767 Max Min Typ Max 14 +1.5 −3.5 ±1.5 +3.5 +2.0 −4.0 +4.0 +0.75 −2.5 ±1.0 +2.5 +1.0 −3.0 +3.0 +0.02 − ...
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... Output −12 dBFS Output −18 dBFS Output Channel Isolation f = 125 MSPS MHz CLK OUT f = 125 MSPS MHz CLK OUT 1 Measured single-ended into 50 Ω load mA, differential transformer-coupled output, 50 Ω OUTFS AD9763 AD9765 Min Typ Max Min Typ Max 125 125 2.5 2.5 2 ...
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... OUTFS Min 3.5 2.1 0 −10 −10 2.0 1.5 3 DATA IN I OUTA OR I OUTB t PD Figure 2. Timing Diagram for Dual and Interleaved Modes Rev Page AD9763/AD9765/AD9767 Typ Max Unit 1.3 V 0.9 V +10 μA +10 μ LPW t ...
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... AD9763/AD9765/AD9767 ABSOLUTE MAXIMUM RATINGS Table 4. With Parameter Respect To AVDD ACOM DVDD1, DVDD2 DCOM1/DCOM2 ACOM DCOM1/DCOM2 AVDD DVDD1/DVDD2 MODE, DCOM1/DCOM2 CLK1/IQCLK, CLK2/IQRESET, WRT1/IQWRT, WRT2/IQSEL Digital Inputs DCOM1/DCOM2 ACOM OUTA1 OUTA2 I /I OUTB1 OUTB2 REFIO, FSADJ1, ACOM FSADJ2 GAINCTRL, SLEEP ACOM Junction Temperature ...
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... PIN 1 DB8P1 2 DB7P1 3 DB6P1 4 DB5P1 5 AD9763 DB4P1 6 TOP VIEW (Not to Scale) DB3P1 7 DB2P1 8 DB1P1 9 DB0P1 (LSB CONNECT Figure 3. AD9763 Pin Configuration DB11P1 (MSB) 1 PIN 1 DB10P1 2 DB9P1 3 DB8P1 4 DB7P1 5 AD9765 DB6P1 6 TOP VIEW (Not to Scale) DB5P1 7 DB4P1 8 DB3P1 9 DB2P1 10 DB1P1 11 DB0P1 (LSB) ...
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... AD9763/AD9765/AD9767 Table 6. Pin Function Descriptions Pin No. AD9763 AD9765 AD9767 14, 13, 14, N 35, 36 15, 21 15, 21 15, 21 16, 22 16 39, 40 39 45, 46 45 Mnemonic Description DBxP1 Data Bit Pins (Port Connect DCOM1, DCOM2 Digital Common DVDD1, DVDD2 Digital Supply Voltage WRT1/IQWRT Input Write Signal for PORT 1 (IQWRT in Interleaving Mode) ...
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... OUT Figure 8. SFDR vs MSPS OUT = 20 mA, 50 Ω doubly terminated load, differential output, T OUTFS f = 125MSPS CLK 100 2.0 2.5 –6dBFS Rev Page AD9763/AD9765/AD9767 = 25°C, SFDR up to Nyquist 0dBFS 75 –6dBFS 70 –12dBFS (MHz) OUT Figure 9. SFDR vs MSPS OUT 80 0dBFS 75 70 – ...
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... AD9763/AD9765/AD9767 85 910kHz/10MSPS 80 2.27MHz/25MSPS 75 70 5.91MHz/65MSPS 65 60 –20 –16 –12 –8 A (dBFS) OUT Figure 12. Single-Tone SFDR vs. A OUT 85 5MHz/25MSPS 80 1MHz/5MSPS 75 2MHz/10MSPS 70 65 13MHz/65MSPS 60 55 –20 –16 –12 –8 A (dBFS) OUT Figure 13. Single-Tone SFDR vs. A OUT 80 3.38MHz/3.36MHz @ 25MSPS 0.965MHz/1.035MHz @ 7MSPS 75 6.75MHz/7.25MHz @ 65MSPS ...
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... MSPS CLK 125 MSPS Rev Page AD9763/AD9765/AD9767 FREQUENCY (MHz) Figure 21. Dual-Tone SFDR @ f = 125 MSPS CLK FREQUENCY (MHz) Figure 22. Four-Tone SFDR @ f = 125 MSPS CLK 40 40 ...
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... AD9763/AD9765/AD9767 AD9765 AVDD = 3 DVDD = 3 Nyquist, unless otherwise noted 5MSPS CLK f = 25MSPS CLK 65MSPS CLK (MHz) OUT Figure 23. SFDR vs dBFS OUT 95 90 0dBFS 85 –6dBFS 80 75 1.00 1.25 1.50 1.75 f (MHz) OUT Figure 24. SFDR vs MSPS OUT 90 85 0dBFS 80 –6dBFS (MHz) OUT Figure 25. SFDR vs. f ...
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... CLK 0.05 0 –0.05 –0.10 –0.15 –0.20 –0.25 –0.30 –0. CLK Rev Page AD9763/AD9765/AD9767 = 20mA I = 10mA OUTFS I = 5mA OUTFS 100 120 f (MSPS) CLK and MHz and 0 dBFS CLK OUTFS OUT 1000 2000 3000 CODE Figure 33. Typical INL ...
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... AD9763/AD9765/AD9767 1MHz OUT 10MHz OUT 25MHz OUT 40MHz 60 OUT 60MHz OUT 50 45 –60 –40 – TEMPERATURE (°C) Figure 35. SFDR vs. Temperature @ 125 MSPS, 0 dBFS 0.05 0.03 GAIN ERROR OFFSET ERROR 0 –0.03 –0.05 –40 – TEMPERATURE (°C) Figure 36. Gain and Offset Error vs. Temperature @ f ...
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... OUT 90 0dBFS 85 –12dBFS –6dBFS (MHz) OUT Figure 42. SFDR vs MSPS OUT = 20 mA, 50 Ω doubly terminated load, differential output, T OUTFS = 125MSPS 100 –6dBFS 2.0 2 Rev Page AD9763/AD9765/AD9767 = 25°C, SFDR 0dBFS 75 –6dBFS 70 –12dBFS (MHz) OUT Figure 43. SFDR vs MSPS OUT 85 80 0dBFS 75 70 –6dBFS –12dBFS ...
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... AD9763/AD9765/AD9767 90 910kHz/10MSPS 85 2.27MHz/25MSPS 11.37MHz/125MSPS 65 5.91MHz/65MSPS Figure 46. Single-Tone SFDR vs. A OUT 90 1MHz/5MSPS 85 2MHz/10MSPS 80 75 5MHz/25MSPS 70 65 13MHz/65MSPS –20 –15 –10 A (dBFS) OUT Figure 47. Single-Tone SFDR vs. A OUT 85 0.965MHz/1.035MHz@7MSPS 80 3.38MHz/3.63MHz@25MSPS 16.9MHz/18.1MHz@125MSPS 60 6.75MHz/7.25MHz@65MSPS 55 50 –25 –20 –15 –10 A (dBFS) OUT Figure 48. Dual-Tone SFDR vs. A OUT ...
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... MSPS CLK Rev Page AD9763/AD9765/AD9767 FREQUENCY (MHz) Figure 55. Dual-Tone SFDR @ f = 125 MSPS CLK FREQUENCY (MHz) Figure 56. Four-Tone SFDR @ f = 125 MSPS CLK 40 40 ...
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... AD9763/AD9765/AD9767 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code ...
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... NOTES 1. IN THIS CONFIGURATION, THE 22nF CAPACITOR AND 256Ω RESISTOR ARE NOT REQUIRED BECAUSE R FUNCTIONAL DESCRIPTION Figure 58 shows a simplified block diagram of the AD9763/ AD9765/AD9767. The AD9763/AD9765/AD9767 consist of two DACs, each one with its own independent digital control logic and full-scale output current control. Each DAC contains ...
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... AVDD operates in the two-resistor, independent gain control mode. AD9763/ SETTING THE FULL-SCALE CURRENT AD9765/ AD9767 REFERENCE Both of the DACs in the AD9763/AD9765/AD9767 contain a SECTION control amplifier that is used to regulate the full-scale output CURRENT SOURCE current (I ARRAY converter, as shown in Figure 59, so that its current output (I ...
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... DAC CODE = 1024/4095/16,384 for the AD9763/AD9765/ AD9767, respectively), while I , the complementary output, OUTB provides no current. The current output appearing function of both the input code and I OUTB AD9763, AD9765, and AD9767, respectively, can be expressed DAC CODE /1024) × I OUTA OUTFS DAC CODE /4096) × I OUTA ...
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... The 10-/12-/14-bit parallel data inputs follow straight binary coding, where the most significant bits (MSBs) are DB9P1 and DB9P2 for the AD9763, DB11P1 and DB11P2 for the AD9765, and DB13P1 and DB13P2 for the AD9767, and the least significant bits (LSBs) are DB0P1 and DB0P2 for all three parts ...
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... Interleaved Mode Timing When the MODE pin is at Logic 0, the AD9763/AD9765/AD9767 operate in interleaved mode (refer to Figure 61). In addition, WRT1 functions as IQWRT, CLK1 functions as IQCLK, WRT2 functions as IQSEL, and CLK2 functions as IQRESET. Data enters the device on the rising edge of IQWRT. The logic level of IQSEL steers the data to either Channel Latch 1 (IQSEL = Channel Latch 2 (IQSEL = 0) ...
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... Logic Level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 × AVDD. This digital input also contains an active pull-down circuit that ensures the AD9763/AD9765/AD9767 remains enabled if this input is left disconnected. The AD9763/AD9765/AD9767 require less than power down and approximately 5 μs to power back up. ...
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... RATIO ( / ) OUT CLK Figure 70. I vs. Ratio @ DVDD1 = DVDD2 = 5 V DVDD Figure 71 Rev Page AD9763/AD9765/AD9767 125MSPS 100MSPS 65MSPS 25MSPS 5MSPS 0.1 0.2 0.3 0.4 0 RATIO ( / ) OUT CLK vs. Ratio @ DVDD1 = DVDD2 = 3.3 V DVDD ...
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... The differential circuit shown in Figure 74 provides the necessary level shifting required in a single-supply system. In this case, AVDD, which is the positive analog supply for both the AD9763/AD9765/AD9767 and the op amp, is used to level shift the differential output of the AD9763/AD9765/AD9767 to midsupply (that is, AVDD/2). The for this application ...
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... OUTB C OPT 25Ω 25Ω Figure 74. Single-Supply DC Differential-Coupled Circuit SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT Figure 75 shows the AD9763/AD9765/AD9767 configured to provide a unipolar output range of approximately 0.5 V for a doubly terminated 50 Ω cable, because the nominal full- scale current ( flows through the equivalent OUTFS Ω. In this case, R ...
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... OUT IN Proper grounding and decoupling are primary objectives in any high speed, high resolution system. The AD9763/AD9765/AD9767 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents . PSRR is very code in a system. In general, decouple the analog supply (AVDD) to the analog common (ACOM) as close to the chip as physically possible ...
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... Figure 81. AD9765 Notch in Missing Bin at 5 MHz Is Down >60 dB –20 –40 –60 –80 –100 0.785 0.805 0.825 –120 Figure 82. AD9767 Notch in Missing Bin at 5 MHz Is Down >60 dB Rev Page AD9763/AD9765/AD9767 –20 –30 –40 –50 –60 –70 –80 –90 0.665 0.685 0.705 ...
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... The circuit implementation shown in Figure 84 helps improve the matching between the I and Q channels, and it shows a path for upconversion using the AD8346 quadrature modulator. The AD9763 provides both I and Q DACs a common reference that improves the gain matching and stability compensate for any mismatch in gain between the two channels ...
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... I and Q digital data can be fed into the AD9763 in two ways. In dual-port mode, the digital I information drives one input port, and the digital Q information drives the other input port interpolation filter precedes the DAC, the symbol rate is the rate at which the system clock drives the CLK and WRT pins on the AD9763 ...
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... INCK2 10 Figure 86. Power Decoupling and Clocks on AD9763/AD9765/AD9767 Evaluation Board (1) This board allows the user the flexibility to operate the AD9763/ AD9765/AD9767 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and single-ended and differential outputs. The digital inputs can be used in dual-port or interleaved mode and are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination ...
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... CC0805 CC0805 Figure 87. Power Decoupling and Clocks on AD9763/AD9765/AD9767 Evaluation Board (2) Rev Page AD9763/AD9765/AD9767 RC0603 RC0805 RC0805 RC0805 RC0805 RC0805 00617-091 ...
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... C30 2 C26 100PF C25 100PF DNP R26 51 C32 RC0603 DNP JP20 CC0805 DNP R25 51 R24 RC0603 Figure 88. Modulator on AD9763/AD9765/AD9767 Evaluation Board Rev Page DNP DNP RC0603 MODULATED OUTPUT AGND2;3,4,5 R27 0 SMAEDGE C28 J1 RC0603 100PF AVDD2 2 TP6 RED AVDD2 R28 1K AGND2 TP5 ...
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... RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RIBBON RA Figure 89. Digital Input Signaling (1) Rev Page AD9763/AD9765/AD9767 00617-093 ...
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... AD9763/AD9765/AD9767 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RIBBON RA Figure 90. Digital Input Signaling (2) Rev Page 00617-087 ...
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... CC0805 CC0805 RC07CUP RC0805 RC0805 Figure 91. Device Under Test/Analog Output Signal Conditioning Rev Page AD9763/AD9765/AD9767 RC07CUP RC0805 RC0805 00617-088 ...
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... AD9763/AD9765/AD9767 EVALUATION BOARD LAYOUT Figure 92. Assembly, Top Side Rev Page ...
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... Figure 93. Assembly, Bottom Side Rev Page AD9763/AD9765/AD9767 ...
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... AD9765ASTRL –40°C to +85°C AD9765ASTZ 1 –40°C to +85°C 1 AD9765ASTZRL –40°C to +85°C AD9767ASTZ 1 –40°C to +85°C 1 AD9767ASTZRL –40°C to +85°C 1 AD9763-EBZ 1 AD9765-EBZ AD9767-EBZ RoHS Compliant Part. 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0.45 48 ...
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... NOTES AD9763/AD9765/AD9767 Rev Page ...
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... AD9763/AD9765/AD9767 NOTES ©1999-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00617-0-6/09(F) Rev Page ...