AD9854/PCB Analog Devices Inc, AD9854/PCB Datasheet
AD9854/PCB
Specifications of AD9854/PCB
Related parts for AD9854/PCB
AD9854/PCB Summary of contents
Page 1
FEATURES 300 MHz internal clock rate FSK, BPSK, PSK, chirp, AM operation Dual integrated 12-bit digital-to-analog converters (DACs) Ultrahigh speed comparator rms jitter Excellent dynamic performance 80 dB SFDR at 100 MHz (±1 MHz) A OUT 4× to ...
Page 2
AD9854 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications..................................................................................... 5 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 Explanation of Test Levels ........................................................... 8 ESD Caution.................................................................................. ...
Page 3
REVISION HISTORY 7/07—Rev Rev. E Changed AD9854ASQ to AD9854ASVZ ....................... Universal Changed AD9854AST to AD9854ASTZ......................... Universal Changes to General Description .....................................................4 Changes to Table 1 Endnotes...........................................................7 Changes to Absolute Maximum Ratings Section..........................8 Changes to Power Dissipation Section.........................................40 Changes ...
Page 4
AD9854 GENERAL DESCRIPTION The AD9854 digital synthesizer is a highly integrated device that uses advanced DDS technology, coupled with two internal high speed, high performance quadrature DACs to form a digitally programmable I and Q synthesizer function. When referenced to ...
Page 5
SPECIFICATIONS V = 3.3 V ± 5 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9854ASVZ, S SET external reference clock frequency = 20 MHz with REFCLK multiplier enabled at ...
Page 6
AD9854 Parameter Residual Phase Noise ( MHz, External Clock = 30 MHz OUT REFCLK Multiplier Engaged at 10×) 1 kHz Offset 10 kHz Offset 100 kHz Offset ( MHz, External Clock = 300 MHz, OUT REFCLK ...
Page 7
Parameter PARALLEL I/O TIMING CHARACTERISTICS t (Address Setup Time to WR Signal Active) ASU t (Address Hold Time to WR Signal Inactive) ADHW t (Data Setup Time to WR Signal Inactive) DSU t (Data Hold Time to WR Signal Inactive) ...
Page 8
AD9854 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature V S Digital Inputs Digital Output Current Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Maximum Clock Frequency (ASVZ) Maximum Clock Frequency (ASTZ) Stresses above those listed ...
Page 9
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVDD DVDD DGND DGND NC A2/IO RESET A1/SDO A0/SDIO I/O UD CLK CONNECT Table 4. Pin Function Descriptions Pin No. Mnemonic 10, 23, 24, 25, ...
Page 10
AD9854 Pin No. Mnemonic 20 I/O UD CLK 21 WR/SCLK 22 RD/CS 29 FSK/BPSK/HOLD 30 OSK AVDD 31, 32, 37, 38, 44, 50, 54, 60, 65 33, 34, 39, 40, 41, AGND 45, 46, 47, 53, 59, 62, 66, 67 ...
Page 11
AVDD AVDD I I OUT OUTB MUST TERMINATE OUTPUTS FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING. A. DAC OUTPUTS B. COMPARATOR OUTPUT AVDD VINP/ VINN COMPARATOR OUT C. COMPARATOR INPUT Figure 3. Equivalent Input and Output ...
Page 12
AD9854 TYPICAL PERFORMANCE CHARACTERISTICS Figure 4 to Figure 9 indicate the wideband harmonic distortion performance of the AD9854 from 19.1 MHz to 119.1 MHz fundamental output, reference clock = 30 MHz, REFCLK multiplier = 10×. Each graph is plotted from ...
Page 13
Figure 10 to Figure 15 show the trade-off in elevated noise floor, increased phase noise (PN), and discrete spurious energy when the internal REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown. ...
Page 14
AD9854 Figure 16 and Figure 17 show the narrow-band performance of the AD9854 when operating with a 200 MHz reference clock with the REFCLK multiplier bypassed vs MHz reference clock and the REFCLK multiplier enabled at 10×. 0 ...
Page 15
RISE TIME 1.04ns JITTER [10.6ps RMS] –33ps 0ps 500ps/DIV 232mV/DIV 50 Ω INPUT Figure 22. Typical Comparator Output Jitter, 40 MHz A 300 MHz RFCLK with REFCLK Multiplier Bypassed REF1 RISE 1.174ns C1 FALL 1.286ns CH1 500mVΩ M 500ps CH1 ...
Page 16
AD9854 TYPICAL APPLICATIONS RF/IF INPUT I BASEBAND Q BASEBAND VCA FUNDAMENTAL LPF COS LPF CHANNEL AD9854 SELECT FILTERS LPF REFCLK SIN LPF Figure 25. Quadrature Downconversion COS LPF AD9854 REFCLK LPF SIN Figure 26. Direct Conversion Quadrature ...
Page 17
REFERENCE CLOCK PHASE LOOP COMPARATOR FILTER FILTER REF CLK IN AD9854 DAC OUT DDS PROGRAMMABLE DIVIDE-BY-N FUNCTION (WHERE TUNING WORD Figure 29. Programmable Fractional Divide-by-N Synthesizer REF CLOCK AD9854 FILTER PHASE DDS COMPARATOR TUNING DIVIDE-BY-N WORD Figure ...
Page 18
AD9854 REFERENCE CLOCK AD9854 8-BIT PARALLEL OR µPROCESSOR/ SERIAL PROGRAMMING CONTROLLER DATA AND CONTROL FPGA, ETC. SIGNALS 300MHz MAX DIRECT MODE OR 15MHz TO 75MHz REFERENCE MAX IN THE 4× TO 20× CLOCK CLOCK MULTIPLIER MODE 2kΩ R SET Figure ...
Page 19
THEORY OF OPERATION The AD9854 quadrature output digital synthesizer is a highly flexible device that addresses a wide range of applications. The device consists of an NCO with a 48-bit phase accumulator, a programmable reference clock multiplier, inverse sinc filters, ...
Page 20
AD9854 F1 MODE 000 (DEFAULT) TW1 MASTER RESET I/O UD CLK As with all Analog Devices DDS devices, the value of the frequency tuning word is determined by FTW = (Desired Output Frequency × 2 where the phase ...
Page 21
000 (DEFAULT) MODE TW1 0 TW2 0 I/O UD CLK FSK DATA (PIN 29) Figure 36. Unramped (Traditional) FSK Mode MODE 000 (DEFAULT) TW1 0 TW2 0 DFW I/O UD CLK FSK DATA (PIN ...
Page 22
AD9854 Frequency ramping, whether linear or nonlinear, necessitates that many intermediate frequencies between F1 and F2 are output in addition to the primary F1 and F2 frequencies. Figure 37 and Figure 38 depict the frequency vs. time characteristics of a ...
Page 23
MODE FSK DATA TRIANGLE I/O UD CLK 000 (DEFAULT) MODE TW1 0 TW2 0 I/O UD CLK FSK DATA Figure 41 shows that premature toggling causes the ramp to immediately reverse itself and proceed at the same ...
Page 24
AD9854 the 32-bit internal update clock (see the Internal and External Update Clock section). Nonlinear ramped FSK has the appearance of the chirp function shown in Figure 43. The difference between a ramped FSK function and a chirp function is ...
Page 25
The AD9854 permits precise, internally generated linear, or externally programmed nonlinear, pulsed or continuous FM over the complete frequency range, duration, frequency resolution, and sweep direction(s). All of these are user programmable. Figure 44 shows a block diagram of the ...
Page 26
AD9854 F1 0 000 (DEFAULT) MODE 0 FTW1 DFW RAMP RATE I/O UD CLK CLR ACC1 F1 0 000 (DEFAULT) MODE TW1 0 DPW RAMP RATE CLR ACC2 I/O UD CLK 011 (CHIRP) F1 DELTA FREQUENCY WORD RAMP RATE Figure ...
Page 27
F1 0 000 (DEFAULT) MODE TW1 0 DFW RAMP RATE HOLD I/O UD CLK 360 0 000 (DEFAULT) MODE FTW1 PHASE ADJUST 1 PHASE ADJUST 2 BPSK DATA I/O UD CLK The 32-bit automatic I/O update counter can be used ...
Page 28
AD9854 • Continue chirp by immediately returning to the beginning frequency (F1 sawtooth fashion, and then repeating the previous chirp process using the CLR ACC1 control bit. An automatic, repeating chirp can be set up by using the ...
Page 29
USING THE AD9854 INTERNAL AND EXTERNAL UPDATE CLOCK This update clock function is comprised of a bidirectional I/O pin (Pin 20) and a programmable 32-bit down-counter. To program changes that are to be transferred from the I/O buffer registers to ...
Page 30
AD9854 DIGITAL SIGNAL IN DDS DIGITAL OUTPUT USER-PROGRAMMABLE Figure 50. Block Diagram of Q DAC Pathway of the Digital Multiplier Section Responsible for the Output Shaped Keying Function The two fixed elements of the transition time are the period of ...
Page 31
INVERSE SINC FUNCTION The inverse sinc function precompensates input data to both DACs for the sin(x)/x roll-off characteristic inherent in the DAC’s output spectrum. This allows wide bandwidth signals (such as QPSK output from the DACs without appreciable ...
Page 32
AD9854 PROGRAMMING THE AD9854 The AD9854 register layout table (Table 8) contains information for programming the chip for the desired functionality. Although many applications require very little programming to configure the AD9854, some use all 12 accessible register banks. The ...
Page 33
Table 8. Register Layout Parallel Serial Address Address (Hex) (Hex) Bit 7 Bit Phase Adjust Register 1 <13:8> (Bits 15, 14, don’t care) 01 Phase Adjust Register 1 <7:0> Phase Adjust Register 2 <13:8> ...
Page 34
AD9854 PARALLEL I/O OPERATION With the S/P SELECT pin tied high, the parallel I/O mode is active. The I/O port is compatible with industry-standard DSPs and microcontrollers. Six address bits, eight bidirectional data bits, and separate write/read control inputs comprise ...
Page 35
A<5:0> A1 D<7:0> RDHOZ RDLOV t t AHD ADV SPECIFICATION VALUE t 15ns ADV t 5ns AHD t 15ns RDLOV t 10ns RDHOZ Figure 52. Parallel Port Read Timing Diagram A<5:0> A1 D<7:0> ...
Page 36
AD9854 GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases of a serial communication cycle with the AD9854. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9854 coincident with the first ...
Page 37
INSTRUCTION BYTE The instruction byte contains the following information: MSB R —Bit 7 determines whether a read or write data transfer occurs following the instruction byte. Logic high indicates ...
Page 38
AD9854 MSB/LSB TRANSFERS The AD9854 serial port can support MSB- and LSB-first data formats. This functionality is controlled by Bit 1 of Serial Register Bank 20 hex. When this bit is set active high, the AD9854 serial port is in ...
Page 39
INSTRUCTION CYCLE CS SCLK SDIO INSTRUCTION CYCLE CS SCLK SDIO SDO INSTRUCTION CYCLE CS SCLK SDIO INSTRUCTION CYCLE CS SCLK SDIO I ...
Page 40
AD9854 POWER DISSIPATION AND THERMAL CONSIDERATIONS The AD9854 is a multifunctional, high speed device that targets a wide variety of synthesizer and agile clock applications. The numerous innovative features contained in the device each consume incremental power. If enabled in ...
Page 41
Q DAC, and the on-board comparator are disabled. 1400 1200 ALL CIRCUITS ENABLED 1000 800 600 400 200 BASIC CONFIGURATION 100 140 180 FREQUENCY (MHz) NOTES THIS GRAPH ASSUMES THAT THE ...
Page 42
AD9854 EVALUATION BOARD An evaluation board package is available for the AD9854 DDS device. This package consists of a PCB, software, and documentation to facilitate bench analysis of the device’s performance. To ensure optimum dynamic performance from the device, users ...
Page 43
DAC signals to be routed to the filters. If the user wishes to test the filters, the shorting jumpers at W7 and W10 should be removed and 50 Ω test signals should be ...
Page 44
AD9854 output current from and doubles the peak-to- peak output voltage developed across the loads, thus resulting in more robust signals at the comparator inputs. Single-Ended Configuration To connect the high speed comparator in a ...
Page 45
Table 12. AD9854 Customer Evaluation Board (AD9854 PCB > AD9854ASVZ) Reference Item Qty Designator Device 1 3 C1, C2, C45 Capacitor 0805 2 21 C7, C8, C9, C10, Capacitor 0603 C11, C12, C13, C14, C16, C17, C18, C19, ...
Page 46
AD9854 Reference Item Qty Designator Device Primary Secondary 28 4 U4, U5, U6, U7 74HC14 29 3 U8, U9, U10 74HC574 30 1 J11 C36CRPX 31 6 W1, W2, W3, W4, 3-pin header W8, W17 32 10 ...
Page 47
PLLFLT GND3 NC5 DIFFCLKEN AVDD CLKVDD CLKGND GND4 CLK8 REFCLK CLK REFCLK PMODE SPSELECT RESET MRESET OPTGND DVDD6 DVDD DVDD7 DGND6 DGND7 DGND8 DGND9 DVDD DVDD8 DVDD9 COUTGND2 GND COUTGND GND COUTVDD2 AVDD COUTVDD AVDD VOUT NC2 DACDGND2 GND DACDGND ...
Page 48
AD9854 Figure 65. Evaluation Board Schematic Rev Page 00636-069 ...
Page 49
Figure 66. Assembly Drawing Figure 67. Top Routing Layer, Layer 1 Rev Page AD9854 ...
Page 50
AD9854 Figure 68. Power Plane Layer, Layer 3 Figure 69. Ground Plane Layer, Layer 2 Rev Page ...
Page 51
Figure 70. Bottom Routing Layer, Layer 4 Rev Page AD9854 ...
Page 52
... AD9854ASVZ −40°C to +85°C AD9854AST −40°C to +85°C 1 AD9854ASTZ −40°C to +85°C AD9854/PCB RoHS Compliant Part. ©2002–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 16.20 16.00 SQ 14.20 15.80 1 ...