ADN8830-EVAL Analog Devices Inc, ADN8830-EVAL Datasheet
ADN8830-EVAL
Specifications of ADN8830-EVAL
Related parts for ADN8830-EVAL
ADN8830-EVAL Summary of contents
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... Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Thermoelectric Cooler Controller GENERAL DESCRIPTION The ADN8830 is a monolithic controller that drives a thermo- electric cooler (TEC) to stabilize the temperature of a laser diode or a passive component used in telecommunications equipment. 0.01 C ...
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... ADN8830–SPECIFICATIONS Parameter TEMPERATURE STABILITY Long-Term Stability PWM OUTPUT DRIVERS Output Transition Time t Nonoverlapping Clock Delay Output Resistance R Output Voltage Swing OUT A Output Voltage Ripple Output Current Ripple LINEAR OUTPUT AMPLIFIER Output Resistance R R Output Voltage Swing OUT B POWER SUPPLY Power Supply Voltage ...
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... ADN8830ACP-REEL – +85 C ADN8830ACP-REEL7 – +85 C ADN8830-EVAL CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADN8830 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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... Connect as Indicated in the Application Notes Section. Optional Clock Input. If not connected, clock frequency set by FREQ pin. Sets Switching Frequency. Controls Initialization Time for ADN8830 with Capacitor to Ground. Phase Adjusted Clock Output. Phase set from PHASE pin. Can be used to drive SYNCIN of other ADN8830 devices. ...
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... TPC 2. N1 and P1 Fall Time 360 SYNC IN = 1MHz 320 A 280 240 200 160 120 0.4 0.8 1.2 0 VPHASE (V) TPC 3. Clock Phase Shift vs. Phase Voltage REV. C Typical Performance Characteristics–ADN8830 360 320 280 240 200 160 120 TPC 4. Clock Phase Shift vs. Phase Voltage 2.480 ...
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... ADN8830 1,000 150k 990 FREQ 980 970 960 950 940 930 920 –40 –15 10 TEMPERATURE ( C) TPC 7. Switching Frequency vs. Temperature –40 – TEMPERATURE ( C) TPC 8. Offset Voltage vs. Temperature 200 100 0 –100 –200 –300 –400 0 0.2 0.4 0.6 0.8 1.0 1.2 COMMON-MODE VOLTAGE (V) TPC 9. Offset Voltage vs. Common-Mode Voltage ...
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... APPLICATION NOTES Principle of Operation The ADN8830 is a controller for a TEC and is used to set and stabilize the temperature of the TEC. A voltage applied to the input of the ADN8830 corresponds to a target temperature setpoint. The appropriate current is then applied to the TEC to pump heat either to or away from the object whose tem- perature is being regulated ...
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... PHASE pin, which can be set by a simple resistor divider. Phase adjustment allows two or more ADN8830 devices to operate from the same clock frequency and not have all outputs switch simultaneously, which could create an excessive power supply ripple. Details of how to adjust the clock frequency and phase are given in the Setting the Switching Frequency section ...
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... The voltage at THERMIN is R THERM V VREF THERM X where VREF has a typical value of 2.47 V. The ADN8830 control loop will adjust the temperature of the TEC until V equals the voltage at TEMPSET (Pin 4), which X we define Target temperature can be set by SET – V SET ...
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... VREF to ground can establish this voltage easily, although any voltage source, such as a DAC, could be used as well. If phase is not a consideration, for example with a single ADN8830 being used, Pin 29 can be tied to Pin 6, which pro- vides a 1.5 V reference voltage. –10– ...
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... The ADN8830 has a shutdown mode that deactivates the output stage and puts the device into a low current standby state. The current draw for the ADN8830 in shutdown is less than 100 A. The shutdown input, Pin 3, is active low. To shut down the device, Pin 3 should be driven to logic low. Once a logic high is applied, the ADN8830 will reactivate after the delay set by the soft start circuitry ...
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... A faster responding and simpler method is to feed the wave locker signal back to the TEC controller for direct temperature control. The ADN8830 is designed to be compatible with a wave locker controller. Figure 11 shows the basic schematic. The TEMPCTL output from ADN8830 is proportional to the object’s actual temperature ...
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... VLIM should not exceed 1.5 V since this causes improper operation of the output voltage limiting circuitry. Setting VLIM to 1.5 V can be used to deactivate the TEC current without shutting down the ADN8830 in the event of a system failure maximum TEC voltage is not required, VLIM should be con- nected to ground not advisable to leave VLIM floating as this would cause unpredictable output behavior ...
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... Equation 22 with OUT Design Example 3 A TEC is specified with a maximum current of 1.5 A and maxi- mum voltage of 2.5 V. The ADN8830 will be operating from a 3.3 V supply voltage with a 200 kHz clock and a 4.7 µH inductor. (22) The duty cycle of the PWM amplifier at 2 calculated ...
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... OUT A of about 6 mV. External FET Requirements External FETs are required for both the PWM and linear amplifiers that drive OUT A and OUT B from the ADN8830. Although it (kHz) is important to select FETs that can supply the maximum current ...
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... FET is turned on, preventing current from shooting through both simultaneously. The input capacitance ( the FET should not exceed 5 nF. ISS The P1 and N1 outputs from the ADN8830 have a typical output impedance This creates a time constant in combination with C of the external FETs equal to 6 ISS shoot-through does not occur through these FETs, this time constant should remain less than 30 ns ...
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... P LOSS RL Finally, the power dissipated by the ADN8830 is equal to the current used by the device multiplied by the supply voltage. Again, this exact equation is difficult to determine as we have already taken into account some of the current while finding the gate charge loss. A reasonable estimate is to use the Table V ...
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... A minimum bypass capacitance should be placed in close proximity to each component connected to the power supply. This includes Pins 8 and 20 on the ADN8830 and both external PMOS transistors. An additional 0.1 F capacitor should be placed in parallel to each 10 F capacitor to provide bypass for high fre- quency noise ...
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... As most laser diodes are driven from supply recommended the ADN8830 be operated from a separate 3.3 V regulated supply unless higher TEC voltages are required. Operation from 3.3 V also improves efficiency, thus minimizing power dissipation ...
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... V. The voltage divider for V calculated from Equation 43. Design Example 5 A maximum output current limit needs to be set at 1.5 A for a TEC with a maximum voltage rating of 2.5 V. The ADN8830 is powered from 5 V. The TEC resistance is estimated at 1.67 efficiency at 85%. Using Equation 43, the voltage drop across R will be 8 ...
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... and a total gain of 66.7 mV/ . Using an RTD with a temperature coefficient of 0.375 / C will give a THERMIN voltage swing from 1 0 well within the input range of the ADN8830. Using a Resistive Load as a Heating Element The ADN8830 can be used in applications that do not neces- sarily drive a TEC but require only a high current output into a load resistance ...
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... ADN8830 PIN 1 INDICATOR 12 MAX 1.00 0.85 0.80 SEATING PLANE OUTLINE DIMENSIONS 32-Lead Lead Frame Chip Scale Package [LFCSP] (CP-32-1) Dimensions shown in millimeters 5.00 BSC SQ 0.60 MAX 0.50 BSC 4.75 TOP BSC SQ VIEW 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX ...
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... Sheet Changed from REV REV. B. Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated Thermistor Setup section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/03—Data Sheet changed from REV REV. A. Renumbered Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Change to Thermistor Setup section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Change to Figure Change to Figure Change to Figure Update OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 REV. C –23– ADN8830 Page ...
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