AD9980/PCB Analog Devices Inc, AD9980/PCB Datasheet
AD9980/PCB
Specifications of AD9980/PCB
Related parts for AD9980/PCB
AD9980/PCB Summary of contents
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FEATURES 95 MSPS maximum conversion rate 9% or less p-p PLL clock jitter at 95 MSPS Automated offset adjustment 2:1 input mux Power-down via dedicated pin or serial register 4:4:4, 4:2:2, and DDR output format modes Variable output drive strength ...
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AD9980 TABLE OF CONTENTS Analog Interface specifications....................................................... 3 Electrical Characteristics ............................................................. 3 Absolute Maximum Ratings............................................................ 5 Explanation of Test Levels........................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Design Guide................................................................................... 10 General Description................................................................... 10 Digital Inputs .............................................................................. 10 ...
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ANALOG INTERFACE SPECIFICATIONS ELECTRICAL CHARACTERISTICS 1.8 V, DAV Table 1. Parameter Temp RESOLUTION Number of Bits LSB Size DC ACCURACY Differential Nonlinearity 25°C 80 MSPS Conversion Rate ...
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AD9980 Parameter DIGITAL OUTPUTS Output Voltage, High ( Output Voltage, Low ( Duty Cycle, DATACK Output Coding POWER SUPPLY V Supply Voltage D V Supply Voltage DD PV Supply Voltage D DAV Supply Voltage D I ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Parameter DAV DD Analog Inputs REFHI REFCM REFLO Digital Inputs Digital Output Current Functional Temperature Storage Temperature Maximum Junction Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges ...
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AD9980 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V (3.3V AIN0 GND AIN1 V (3.3V AIN0 GND 7 SOGIN0 8 V (3.3V AIN1 GND 11 SOGIN1 12 ...
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Pin Type Mnemonic Function HSOUT Hsync Output Clock (Phase-Aligned with DATACK) VSOUT Vsync Output Clock SOGOUT Sync-on-Green Slicer Output O/E FIELD Odd/Even Field Output References FILT Connection for External Filter Components for Internal PLL REFLO Connection for External Capacitor for ...
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AD9980 Table 4. Pin Function Descriptions Pin Description INPUTS RAIN0 Analog Input for the Red Channel 0. GAIN0 Analog Input for the Green Channel 0. BAIN0 Analog Input for the Blue Channel 0. RAIN1 Analog Input for the Red Channel ...
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Pin Description FILT External Filter Connection. For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 7 to this pin. For optimal performance, minimize noise and parasitics on this node. For more ...
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AD9980 DESIGN GUIDE GENERAL DESCRIPTION The AD9980 is a fully integrated solution for capturing analog RGB or YPbPr signals and digitizing them for display on advanced TVs, flat panel monitors, projectors, and other types of digital displays. Implemented in a ...
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In most PC graphics systems, black is transmitted between active video lines. With CRT displays, when the electron beam has completed writing a horizontal line on the screen (at the right side), the beam is deflected quickly to the left ...
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AD9980 Negative target codes are included in order to duplicate a fea- ture that is present with manual offset adjustment. The benefit that is being mimicked is the ability to easily adjust brightness on a display. By setting the target ...
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PIXEL CLOCK INVALID SAMPLE TIMES Figure 6. Pixel Sampling Times Any jitter in the clock reduces the precision with which the sampling time can be determined and must also be subtracted from the stable pixel time. Considerable care has been ...
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AD9980 Table 9. Recommended VCO Range and Charge Pump and Current Settings for Standard Display Formats Refresh Rate Standard Resolution (Hz) VGA 640 × 480 SVGA 800 × 600 XGA 1024 ...
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HSYNC0 ACTIVITY POLARITY DETECT HSYNC1 ACTIVITY POLARITY DETECT SYNC SOGIN0 SLICER ACTIVITY SYNC SOGIN1 SLICER ACTIVITY VSYNC0 ACTIVITY POLARITY DETECT VSYNC1 ACTIVITY POLARITY DETECT COAST AD9980 Sync Processing The inputs of the sync processing section of the AD9980 are combinations ...
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AD9980 700mV MAXIMUM –300mV SOG INPUT 0mV –300mV SOGOUT OUTPUT CONNECTED TO HSYNCIN COMPOSITE SYNC AT HSYNCIN VSYNCOUT FROM SYNC SEPARATOR Sync Separator As part of sync processing, the sync separator’s task is to extract Vsync from the composite sync ...
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HSYNCIN FILTER WINDOW HSYNCOUT VSYNC Vsync Filter and Odd/Even Fields The Vsync filter is used to eliminate spurious Vsyncs, maintain a stable timing relationship between the Vsync and Hsync output signals, and generate the odd/even field output. The filter works ...
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AD9980 SYNC SEPARATOR THRESHOLD FIELD 1 FIELD 0 QUADRANT HSYNCIN VSYNCIN VSYNCOUT O/E FIELD EVEN FIELD Figure 12. Vsync Filter—Odd/Even Power Management To meet display requirements for low standby power, the AD9980 includes a power-down ...
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TIMING DIAGRAMS The following timing diagrams show the operation of the AD9980.The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to DATACK DATAIN P0 HSIN DATACLK DATAOUT HSOUT ...
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AD9980 DATAIN P0 HSIN DATACLK HSOUT DDR NOTES 1. OUTPUT DATACLK MAY BE DELAYED 1/4 CLOCK PERIOD IN THE REGISTERS. 2. FOR DDR 4:2:2 MODE: TIMING IS IDENTICAL, VALUES OF F (FALLING EDGE) AND R (RISING EDGE) CHANGE. GENERAL NOTES ...
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Mode Descriptions • 4:4:4—All channels come out with their 8 data bits at the same time. Data is aligned to the negative edge of the clock for easy capture. This is the normal 24-bit output mode for RGB or 4:4:4 ...
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AD9980 TWO-WIRE SERIAL REGISTER MAP The AD9980 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is employed to write and read the control registers through the two-wire serial interface port. Table ...
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Read and Hexadecimal Write or Default Address Read Only Bits Value 0x12 R/W 7 0*** **** 6 *0** **** 5 **0* **** 4 ***1 **** 3 **** 1*** 0x13 R/W 7:0 0010 0000 0x14 R/W 7 0*** **** 6 *0** ...
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AD9980 Read and Hexadecimal Write or Default Address Read Only Bits Value 5 **1* **** 4 ***0 **** 3 **** 0*** 2 **** *0** 1 **** **0* 0 **** ***0 0x19 R/W 7:0 0000 1000 0x1A R/W 7:0 0010 0000 ...
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Read and Hexadecimal Write or Default Address Read Only Bits Value 5 **1* **** 4 ***1 **** 3 **** 0*** 2 **** *0** 1 **** **0* 0 **** ***0 0x1F R/W 6:5 *00* **** 4 ***1 **** 3 **** 0*** ...
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AD9980 Read and Hexadecimal Write or Default Address Read Only Bits Value 1 **** **1* 0 **** ***1 0x21 R/W 7:0 0010 0000 0x22 R/W 7:0 0011 0010 0x23 R/W 7:0 0000 1010 0x24 RO 7 _*** **** 6 *_** ...
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Read and Hexadecimal Write or Default Address Read Only Bits Value 0x26 RO 7:0 0x27 RO 7:4 0x28 R/W 7:0 1011 1111 0x29 R/W 7:0 0000 0010 0x2A RO 7:0 0x2B RO 7:0 0x2C R/W 7:5 000* **** 4 ***0 ...
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AD9980 DETAILED 2-WIRE SERIAL CONTROL REGISTER DESCRIPTIONS CHIP IDENTIFICATION 0x00 7:0 Chip Revision An 8-bit register which represents the silicon revision PLL DIVIDER CONTROL 0x01 7:0 PLL Divide Ratio MSBs The eight MSBs of the 12-bit PLL divide ratio PLLDIV. ...
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PHASE ADJUST 0x04 7:3 Phase adjustment for the DLL to generate the ADC clock. A 5-bit value that adjusts the sampling phase in 32 steps across one pixel time. Each step represents an 11.25° shift in sampling phase. The power ...
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AD9980 0x12 7 Hsync Source Override This is the active Hsync override. Setting this to 0 allows the chip to determine the active Hsync source. Setting uses Bit 6 of Register 0x12 to determine the active Hsync ...
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Input Vsync Polarity If Bit 5 of Register 0x14 is 1, the value of this bit specifies the polarity of the input Vsync. Setting this bit to 0 indicates an active low Vsync; setting this bit to 1 ...
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AD9980 0x18 4 Clamp Source This bit determines the source of clamp timing enables the clamp timing circuitry controlled by clamp placement and clamp duration. The clamp posi- tion and duration is counted from the leading edge of ...
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Auto-Offset Enable This bit selects between auto-offset mode and manual offset mode (auto-offset disabled). See the section on auto-offset operation. The power-up default setting is 0. Table 37. Auto-Offset Settings Auto-Offset Result 0 Auto-offset is disabled 1 Auto-offset ...
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AD9980 power-down to be controlled by software. With manual power-down control, the polarity of the power-down pin must be set (0x1E, Bit 2) whether it is used or not. If unused recommended to set the polarity to active ...
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Output Drive Strength These two bits select the drive strength for all high- speed digital outputs (except VSOUT, A0, and the O/E field). Higher drive strength results in faster rise/fall times and in general makes it easier to ...
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AD9980 DETECTION STATUS 0x24 7 Hsync0 Detection Bit This bit is used to indicate when activity is detected on the HSYNC0 input pin. If Hsync is held high or low, activity will not be detected. The sync processing block diagram ...
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Vsync0 Polarity Indicates the polarity of Vsync0 input. Table 70. Detected Vsync0 Polarity Results Detect Result 0 Vsync polarity is negative 1 Vsync polarity is positive 0x25 4 Vsync1 Polarity Indicates the polarity of Vsync1 input. Table 71. ...
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AD9980 TWO-WIRE SERIAL CONTROL PORT A two-wire serial interface control interface is provided two AD9980 devices may be connected to the two-wire serial interface with each device having a unique address. The two-wire serial interface comprises a clock ...
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Serial Interface Read/Write Examples Write to one control register: • Start signal • Slave address byte (R/W\ bit = low) • Base address byte • Data byte to base address • Stop signal Write to four consecutive control registers: • ...
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AD9980 PCB LAYOUT RECOMMENDATIONS The AD9980 is a high-precision, high-speed analog device. To achieve the maximum performance from the part important to have a well laid-out board. The Analog Interface Inputs section contains a guide for designing a ...
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Adding a series resistor of value 50 Ω to 200 Ω can suppress reflections, reduce EMI, and reduce the current spikes inside the AD9980. If series resistors are used, place them as close to the AD9980 pins as possible, (although ...
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... SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 AD9980KSTZ-80 0°C to +70°C 1 AD9980KSTZ-95 0°C to +70°C AD9980/PCB 1 Pb-free part. 0.75 1.60 0.60 MAX 0. SEATING PLANE 10° 6° 0.20 2° 0.09 VIEW A 7° ...
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NOTES Rev Page AD9980 ...
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AD9980 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, ...