AD9511-VCO/PCB Analog Devices Inc, AD9511-VCO/PCB Datasheet
AD9511-VCO/PCB
Specifications of AD9511-VCO/PCB
Related parts for AD9511-VCO/PCB
AD9511-VCO/PCB Summary of contents
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... The AD9511 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9511 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. The temperature range is − ...
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... AD9511 TABLE OF CONTENTS Specifications..................................................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 5 Clock Outputs ............................................................................... 6 Timing Characteristics ................................................................ 7 Clock Output Phase Noise .......................................................... 9 Clock Output Additive Time Jitter........................................... 12 PLL and Distribution Phase Noise and Spurious................... 14 Serial Control Port ..................................................................... 15 FUNCTION Pin ......................................................................... 15 STATUS Pin ................................................................................ 16 Power............................................................................................ 16 Timing Diagrams............................................................................ 17 Absolute Maximum Ratings.......................................................... 18 Thermal Characteristics ...
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... Changes to CLK1 and CLK2 Clock Inputs Section....................33 Summary Table............................................................................45 Register Map Description ..........................................................47 Power Supply ...................................................................................54 Power Management ....................................................................54 Applications .....................................................................................55 Using the AD9511 Outputs for ADC Clock Applications ....55 CMOS Clock Distribution.........................................................55 LVPECL Clock Distribution......................................................56 LVDS Clock Distribution...........................................................56 Power and Grounding Considerations and Power Supply Rejection.......................................................................................56 Outline Dimensions ...
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... AD9511 SPECIFICATIONS Typical (typ) is given for V = 3.3 V ± 5 Minimum (min) and maximum (max) values are given over full V PLL CHARACTERISTICS Table 1. Parameter REFERENCE INPUTS (REFIN) Input Frequency Input Sensitivity Self-Bias Voltage, REFIN Self-Bias Voltage, REFINB Input Resistance, REFIN Input Resistance, REFINB ...
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... Approximation of the PFD/CP phase noise floor (in the flat region) inside the PLL loop bandwidth. When running closed loop this 3 phase noise is gained × log(N) Signal available at STATUS pin when selected by 08h<5:2>. Selected by Register ODh. <5> = 1b. <5> = 0b. <5> = 0b. Selected by Register 0Dh. <5> = 1b. <5> = 0b. <5> = 0b. AD9511 . ...
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... AD9511 CLOCK OUTPUTS Table 3. Parameter LVPECL CLOCK OUTPUTS OUT0, OUT1, OUT2; Differential Output Frequency Output High Voltage ( Output Low Voltage ( Output Differential Voltage ( LVDS CLOCK OUTPUTS OUT3, OUT4; Differential Output Frequency Differential Output Voltage ( Delta V OD Output Offset Voltage ( Delta V OS ...
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... LOAD Delay off on OUT4 ns ns ps/°C Delay off on OUT4 ps ps Everything the same; different logic type ns LVPECL to LVDS on same part Everything the same; different logic type ns LVPECL to CMOS on same part Everything the same; different logic type ps LVDS to CMOS on same part AD9511 ...
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... AD9511 Parameter DELAY ADJUST 4 Shortest Delay Range Zero Scale Full Scale Linearity, DNL Linearity, INL 4 Longest Delay Range Zero Scale Full Scale Linearity, DNL Linearity, INL Delay Variation with Temperature 5 Long Delay Range Zero Scale Full Scale Short Delay Range Zero Scale ...
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... Rev Page AD9511 Test Conditions/Comments Distribution Section only; does not include PLL or external VCO/VCXO Input slew rate > 1 V/ns ...
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... AD9511 Parameter CLK1-TO-LVDS ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT= 622.08 MHz Divide Ratio = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = Offset @ 100 Hz Offset @ 1 kHz Offset ...
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... Rev Page AD9511 Test Conditions/Comments Distribution Section only; does not include PLL or external VCO/VCXO ...
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... AD9511 CLOCK OUTPUT ADDITIVE TIME JITTER Table 6. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = 622.08 MHz Divide Ratio = 1 CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = 155.52 MHz Divide Ratio = 4 CLK1 = 400 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz ...
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... Calculated from SNR of ADC method 100 MHz with A C Interferer(s) Interferer(s) 374 fs rms Calculated from SNR of ADC method 100 MHz with A C Interferer(s) Interferer(s) Rev Page AD9511 = 170 MHz IN = 170 MHz IN = 170 MHz IN = 170 MHz IN = 170 MHz IN = 170 MHz IN = 170 MHz IN ...
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... AD9511 Parameter CLK1 = 400 MHz CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz CMOS (OUT4 MHz (B Output On) 1 DELAY BLOCK ADDITIVE TIME JITTER 100 MHz Output Delay (1600 μA, 1C) Fine Adj. 00000 Delay (1600 μA, 1C) Fine Adj. 11111 Delay (800 μA, 1C) Fine Adj. 00000 Delay (800 μ ...
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... This pin should normally be held high. Do not leave NC. V 0.8 V μA 1 μ High speed clock cycles High speed clock is CLK1 or CLK2, whichever is used for distribution. Rev Page Unit Test Conditions/Comments CSB and SCLK have 30 kΩ internal pull-down resistors V V μA μ MHz AD9511 ...
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... AD9511 STATUS PIN Table 10. Parameter Min OUTPUT CHARACTERISTICS Output Voltage High (V ) 2.7 OH Output Voltage Low ( MAXIMUM TOGGLE RATE ANALOG LOCK DETECT Capacitance POWER Table 11. Parameter POWER-UP DEFAULT MODE POWER DISSIPATION POWER DISSIPATION Full Sleep Power-Down Power-Down (PDB) POWER DELTA CLK1, CLK2 Power-Down Divider, DIV 2 − ...
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... TIMING DIAGRAMS t CLK1 CLK1 t PECL t LVDS t CMOS Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential DIFFERENTIAL 20% SINGLE-ENDED 20 Rev Page 80% LVDS Figure 4. LVDS Timing, Differential 80% CMOS 3pF LOAD Figure 5. CMOS Timing, Single-Ended Load AD9511 ...
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... AD9511 ABSOLUTE MAXIMUM RATINGS Table 12. With Respect to Parameter or Pin VS GND VCP GND VCP V S REFIN, REFINB GND RSET GND CPRSET GND CLK1, CLK1B, CLK2, CLK2B GND CLK1 CLK1B CLK2 CLK2B SCLK, SDIO, SDO, CSB GND OUT0, OUT1, OUT2, OUT3, GND OUT4 ...
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... Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground, GND. REFIN 1 PIN 1 INDICATOR REFINB VCP AD9511 VS 6 CLK2 7 TOP VIEW (Not to Scale) CLK2B CLK1 10 CLK1B 11 12 Figure 6. 48-Lead LFCSP Pin Configuration Rev Page AD9511 OUT3 34 OUT3B OUT4 30 OUT4B OUT1 26 OUT1B 25 VS ...
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... AD9511 Table 13. Pin Function Descriptions Pin No. Mnemonic Description 1 REFIN PLL Reference Input. 2 REFINB Complementary PLL Reference Input 18, 22, VS Power Supply (3.3 V). 23, 25, 28, 29, 32, 33, 36, 39, 40, 44 VCP Charge Pump Power Supply. It should be greater than or equal to VS. VCP can be set as high as 5.5 V for VCOs, requiring extended tuning range. ...
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... In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev Page AD9511 ...
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... AD9511 TYPICAL PERFORMANCE CHARACTERISTICS 0.6 DEFAULT – 3 LVPECL + 2 LVDS (DIV ON) 0.5 3 LVPECL + 2 LVDS (DIV BYPASSED) 0.4 3 LVPECL (DIV ON) 2 LVDS (DIV ON) 0.3 0 400 OUTPUT FREQUENCY (MHz) Figure 7. Power vs. Frequency—LVPECL, LVDS (PLL Off) CLK1 (EVAL BOARD) 3GHz 5MHz Figure 8. CLK1 Smith Chart (Evaluation Board) ...
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... V Figure 17. Charge Pump Output Characteristics @ VCP S Rev Page 30kHz/ SPAN 300kHz 1 10 PFD FREQUENCY (MHz) PUMP DOWN PUMP UP 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VOLTAGE ON CP PIN (V) AD9511 100 4.5 5 ...
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... AD9511 VERT 500mV/DIV Figure 18. LVPECL Differential Output @ 800 MHz VERT 100mV/DIV Figure 19. LVDS Differential Output @ 800 MHz VERT 500mV/DIV Figure 20. CMOS Single-Ended Output @ 250 MHz with 10 pF Load 1.8 1.7 1.6 1.5 1.4 1.3 1.2 100 HORIZ 500ps/DIV Figure 21. LVPECL Differential Output Swing vs. Frequency ...
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... Figure 28. Additive Phase Noise—LVDS DIV2, 122.88 MHz –100 –110 –120 –130 –140 –150 –160 –170 1M 10M 10 Figure 29. Additive Phase Noise—CMOS DIV4, 61.44 MHz Rev Page AD9511 100 1k 10k 100k 1M OFFSET (Hz) 100 1k 10k 100k 1M OFFSET (Hz) 100 1k 10k 100k 1M ...
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... TYPICAL MODES OF OPERATION PLL WITH EXTERNAL VCXO/VCO FOLLOWED BY CLOCK DISTRIBUTION This is the most common operational mode for the AD9511. An external oscillator (shown as VCO/VCXO) is phase locked to a reference input frequency applied to REFIN. The loop filter is usually a passive design. A VCO or a VCXO can be used. The CLK2 input is connected internally to the feedback divider, N ...
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... REFIN REFERENCE R INPUT PFD N FUNCTION STATUS CLK1 LVPECL DIVIDE LVPECL DIVIDE LVPECL DIVIDE LVDS/CMOS SERIAL PORT DIVIDE LVDS/CMOS Δ DIVIDE T Figure 32. AD9511 with VCO and BPF Filter PLL REF CHARGE LOOP PUMP FILTER CLK2 VCO BPF CLOCK OUTPUTS Rev Page AD9511 ...
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... AD9511 REFIN 250MHz REFINB FUNCTION CLK1 1.6GHz CLK1B SCLK SDIO SDO CSB VS GND RSET DISTRIBUTION AD9511 REF R DIVIDER PHASE FREQUENCY DETECTOR N DIVIDER SYNCB, RESETB PDB PROGRAMMABLE DIVIDERS AND PHASE ADJUST /1, /2, /3... /31, /32 /1, /2, /3... /31, /32 /1, /2, /3... /31, /32 SERIAL CONTROL /1, /2, /3... /31, /32 PORT /1, /2, /3 ...
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... REFIN and CLK2, and a different control register architecture. Also, the prescaler has been changed to allow N as low as 1. The AD9511 PLL implements the digital lock detect feature somewhat differently than the ADF4106 does, offering improved functionality at higher PFD rates. See the Register Map Description section. PLL Reference Input— ...
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... A and B Counters The AD9511 B counter has a bypass mode (B = 1), which is not available on the ADF4106. The B counter bypass mode is valid Divide By only when using the prescaler in FD mode. The B counter is 1 bypassed by writing 1 to the B counter bypass bit (0Ah<6> 1b). The valid range of the B counter 8191. The default P 2/3 after a reset is 0, which is invalid ...
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... VCO signal. STATUS Pin V P The output multiplexer on the AD9511 allows access to various CHARGE signals and internal points on the chip at the STATUS pin. PUMP Figure 37 shows a block diagram of the STATUS pin section. ...
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... The loss-of-reference circuit is clocked by the signal from the VCO, which means that there must be a VCO signal present to detect a loss of reference. The digital lock detect (DLD) block of the AD9511 requires a PLL reference signal to be present for the digital lock detect output to be valid possible to have a digital lock detect indication (DLD = true) that remains true even after a loss-of- reference signal ...
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... DIVIDERS Each of the five clock outputs of the AD9511 has its own divider. The divider can be bypassed to get an output at the same frequency as the input (1×). When a divider is bypassed powered down to save power ...
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... AD9511 Table 17. Duty Cycle and Divide Ratio LO<7:4> Divide Ratio Duty Cycle (%) 4Ah to 52h HI<3:0> Divide Ratio Rev Page 4Ah to 52h LO<7:4> HI<3:0> Duty Cycle (%) ...
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... LO<7:4> Divide Ratio Duty Cycle (%) 4Ah to 52h HI<3:0> Divide Ratio Rev Page AD9511 4Ah to 52h LO<7:4> HI<3:0> Duty Cycle (%) ...
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... AD9511 LO<7:4> Divide Ratio Duty Cycle (%) 4Ah to 52h HI<3:0> Divide Ratio Rev Page 4Ah to 52h LO<7:4> HI<3:0> Duty Cycle (%) ...
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... For any divide ratio, the number of unique phase offsets is numerically equal to the divide ratio (see Table 18): DIV = 4 Unique Phase Offsets Are Phase = DIV= 7 Unique Phase Offsets Are Phase = Rev Page AD9511 4Bh to 53h Phase Offset <3:0> Start H/L <4> ...
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... Fine_Adj = Value of Delay Fine Adjust (Register 36h or Register 3Ah <5:1>), that is, 11111 = 31 Delay (ns) = Offset + Delay_Range × Fine_adj × (1/31) OUTPUTS The AD9511 offers three different output level choices: LVDS LVPECL, LVDS, and CMOS. OUT0 to OUT2 are LVPECL only. OUTPUT OUT3 and OUT4 can be selected as either LVDS or CMOS. ...
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... Chip Power-Down or Sleep Mode—PDB The PDB chip power-down turns off most of the functions and currents in the AD9511. When the PDB mode is enabled, a chip power-down is activated by taking the FUNCTION pin to a logic low level. The chip remains in this power-down state until PDB is brought back to logic high ...
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... CLK2 (or REFIN) input of the slave. Multichip synchronization is enabled by writing to Register 58h<0> the slave AD9511. When this bit is set, the STATUS pin becomes the output for the SYNC signal. A low signal indicates an in-sync condition, and a high indicates an out-of-sync condition. Register 58h< ...
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... If the instruction word is for a write operation (I15 = 0b), the second part is the transfer of data into the serial control port buffer of the AD9511. The length of the transfer ( bytes or streaming mode) is indicated by two bits (W1:W0) in the instruction byte. CSB can be raised after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle) ...
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... MSB/LSB FIRST TRANSFERS The AD9511 instruction word and byte data may be MSB first or LSB first. The default for the AD9511 is MSB first. The LSB first mode may be set by writing 1b to Register 00h<6>. This takes effect immediately (since it only affects the operation of the serial control port) and does not require that an update be executed ...
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... Figure 49. Timing Diagram for Serial Control Port Register Read REGISTER (N) DATA Rev Page REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA t H DON'T CARE DON'T CARE REGISTER ( DATA AD9511 LSB DON'T CARE DON'T CARE DON'T CARE DON'T CARE DON'T CARE DON'T CARE ...
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... AD9511 t S CSB t DS SCLK SDIO BI N Table 22. Serial Control Port Timing Parameter Description t Setup time between data and rising edge of SCLK DS t Hold time between data and rising edge of SCLK DH t Period of the clock CLK t Setup time between CSB and SCLK ...
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... REGISTER MAP AND DESCRIPTION SUMMARY TABLE Table 23. AD9511 Register Map Addr (Hex) Parameter Bit 7 (MSB) 00 Serial SDO Inactive Control Port (Bidirectional Configuration Mode) 01, 02, 03 PLL 04 A Counter Not Used 05 B Counter Not Used 06 B Counter 07 PLL 1 Not Used 08 PLL 2 Not Used ...
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... AD9511 Addr (Hex) Parameter Bit 7 (MSB) OUTPUTS 3D LVPECL OUT0 3E LVPECL OUT1 3F LVPECL OUT2 40 LVDS_CMOS Not Used OUT 3 41 LVDS_CMOS Not Used OUT 4 42, 43, 44 CLK1 AND CLK2 45 Clocks Select, Not Used Power-Down (PD) Options 46, 47, 48, 49 DIVIDERS 4A Divider 0 4B Divider 0 Bypass 4C Divider 1 ...
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... REGISTER MAP DESCRIPTION Table 24 lists the AD9511 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by angle brackets. For example, <3> refers to Bit 3, while <5:2> refers to the range of bits from Bit 5 through Bit 2. Table 24 describes the functionality of the control registers on a bit-by-bit basis. For a more concise (but less descriptive) table, see Table 23. ...
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... AD9511 Reg. Addr. (Hex) Bit(s) Name 08 <5:2> PLL Mux Control 08 <6> Phase-Frequency Detector (PFD) Polarity 08 <7> 09 <0> Reset All Counters 0 = Normal (Default Reset R, A, and B Counters. 09 <1> N-Counter Reset 09 <2> R-Counter Reset 09 <3> 09 <6:4> Charge Pump (CP) Current Setting 09 <7> Description <5> ...
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... Mode Prescaler Mode Divide Divide 16/ 32/ Divide by 3 <0> Digital Lock Detect Window (ns) Digital Lock Detect Loss-of-Lock Threshold (ns) 9.5 15 3.5 7 Rev Page AD9511 Mode Normal Operation Asynchronous Power-Down Normal Operation Synchronous Power-Down Antibacklash Pulse Width (ns) 1.3 (Default) 2.9 6.0 1.3 ...
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... AD9511 Reg. Addr. (Hex) Bit(s) Name Fine Delay Adjust 34 <0> Delay Control OUT4 34 <7:1> 35 <2:0> Ramp Current OUT4 35 <5:3> Ramp Capacitor OUT4 35 <7:6> 36 <0> 36 <5:1> Delay Fine Adjust OUT4 36 <7:6> <7:0> 37 (38) (39) (3A) (3B) (3C) 3D (3E) (3F) <1:0> Power-Down LVPECL OUT0 (OUT1) (OUT2) Description Delay Block Control Bit ...
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... Power-Down CLK1 and CLK2 Inputs and Associated Bias and Internal Clock Tree; Power-Down (Default = 0b). 45 <7:6> Not Used. 46 (47) <7:0> Not Used. (48) (49) <2> <1> Current (mA) 0 1.75 1 3.5 (Default Rev Page AD9511 Output Voltage (mV) 490 330 805 (Default) 650 Termination (Ω) 100 100 50 50 ...
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... AD9511 Reg. Addr. (Hex) Bit(s) Name <3:0> Divider High 4A OUT0 (4C) (OUT1) (4E) (OUT2) (50) (OUT3) (52) (OUT4) <7:4> Divider Low 4A OUT0 (4C) (OUT1) (4E) (OUT2) (50) (OUT3) (52) (OUT4) <3:0> Phase Offset 4B OUT0 (4D) (OUT1) (4F) (OUT2) (51) (OUT3) (53) (OUT4) <4> Start 4B OUT0 (4D) (OUT1) (4F) (OUT2) (51) (OUT3) (53) (OUT4) <5> Force 4B OUT0 (4D) ...
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... SCLK edge. This is a self-clearing bit. 0 does not have to be written to clear it. 5A <7:1> Not Used. END <5> Rev Page AD9511 Function RESETB (Default) SYNCB Test Only; Do Not Use PDB ...
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... The PCB acts as a heat sink for the AD9511; therefore, this GND connection should provide a good thermal path to a larger dissipation area, such as a ground plane on the PCB. See the layout of the AD9511 evaluation board (AD9511/PCB or AD9511-VCO/PCB) for a good example. POWER MANAGEMENT . ...
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... Termination at the far end of the PCB trace is a second option. 8 The CMOS outputs of the AD9511 do not supply enough 6 current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in Figure 55. The far- 4 end termination network should match the PCB trace ...
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... Figure 57. LVPECL with Parallel Transmission Line LVDS CLOCK DISTRIBUTION Low voltage differential signaling (LVDS second differential output option for the AD9511. LVDS uses a current mode output stage with several user-selectable current levels. The normal value (default) for this current is 3.5 mA, which yields 350 mV output swing across a 100 Ω ...
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... MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9511BCPZ −40°C to +85°C 1 AD9511BCPZ-REEL7 −40°C to +85°C AD9511/PCB AD9511-VCO/PCB Pb-free part. 0.60 MAX 37 36 6.75 BSC SQ 0.50 0. 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0 ...
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... AD9511 NOTES Rev Page ...
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... NOTES Rev Page AD9511 ...
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... AD9511 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05286–0–6/05(A) Rev Page ...