AD9444-LVDS/PCB Analog Devices Inc, AD9444-LVDS/PCB Datasheet
AD9444-LVDS/PCB
Specifications of AD9444-LVDS/PCB
Related parts for AD9444-LVDS/PCB
AD9444-LVDS/PCB Summary of contents
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... Figure 1. Optional features allow users to implement various selectable operating conditions, including data format select and output data mode. The AD9444 is available in a 100-lead surface-mount plastic package (100-lead TQFP/EP) specified over the industrial temperature range (−40°C to +85°C). PRODUCT HIGHLIGHTS 1. High performance: Outstanding SFDR performance for mul- ticarrier, multimode 3G and 4G cellular base station receivers ...
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... AD9444 TABLE OF CONTENTS DC Specifications ............................................................................. 3 AC Specifications.............................................................................. 4 Digital Specifications........................................................................ 5 Switching Specifications .................................................................. 6 Explanation of Test Levels........................................................... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Definitions of Specifications ........................................................... 9 Pin Configurations and Function Descriptions ......................... 10 Equivalent Circuits ......................................................................... 14 Typical Performance Characteristics ........................................... 15 Theory of Operation ...................................................................... 20 Analog Input and Reference Overview ................................... 20 REVISION HISTORY 10/04—Revision 0: Initial Version Clock Input Considerations ...
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... Sine Wave Input 2 —CMOS Outputs 1 The internal voltage reference is trimmed at final test to minimize the gain error of the AD9444. 2 Measured at the maximum clock rate MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and IN approximately 5 pF loading on each output bit for CMOS output mode ...
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... IV 25°C I Full IV 25°C IV Full IV 25°C V 25°C IV Full IV 25°C I Full IV 25°C IV Full IV 25°C V 25°C V 25°C V Full V Rev Page AD9444BSVZ-80 Unit Typ Max 72 72.3 dB 12.1 Bits 12.0 Bits 11.9 Bits 11 ...
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... Temp Test Level Full IV Full IV Full VI Full VI Full V 1 Full IV Full IV Full VI Full VI Full IV Full VI Full V Full V Rev Page AD9444 AD9444BSVZ-80 Min Typ Max Unit 2.0 V 0.8 V +200 µA −10 +10 µ 3.25 V 0.2 V 247 545 mV 1.125 1.375 V 0.2 V 1.3 1.5 1.6 ...
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... DCO– t CPD Temp Full Full Full Full Full 2 ) (DX, DCO+) Full 3 ) (DX+, DCO+) Full Full Full Full N N–12 N–11 12 CLOCK CYCLES Figure 2. LVDS Mode Timing Diagram Rev Page AD9444BSVZ-80 Test Level Min Typ Max 0.2 N+1 Unit MSPS MSPS ...
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... Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range. N+1 N+2 12 CYCLES N-12 N-11 N-1 Figure 3. CMOS Timing Diagram Rev Page DCOPD AD9444 ...
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... Although this product features proprie- tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Thermal Resistance The heat sink of the AD9444 package must be soldered to Max Unit ground. Table 6. ...
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... The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Rev Page AD9444 ) PD ...
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... AVDD2 19 AGND 20 VIN+ 21 VIN– 22 AGND 23 AVDD1 24 AVDD1 25 DNC = DO NOT CONNECT AD9444 TOP VIEW (Not to Scale) Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode Rev Page DRVDD 74 DRGND 73 D10+ 72 D10– 71 D9+ 70 D9– 69 D8+ 68 D8– 67 DRGND 66 D7+ 65 D7– 64 DCO+ 63 DCO– ...
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... D13− 81 D13+ (MSB) 84 OR− 85 OR+ 100 DCS MODE Rev Page AD9444 Description D0 True Output Bit. D1 Complement Output Bit. D1 True Output Bit. 3.3 V Digital Output Supply (3 3.6 V). Digital Ground. D2 Complement Output Bit. D2 True Output Bit. D3 Complement Output Bit. D3 True Output Bit. ...
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... AVDD1 16 AVDD1 17 AVDD1 18 AVDD2 19 AGND 20 VIN+ 21 VIN– 22 AGND 23 AVDD1 24 AVDD1 25 DNC = DO NOT CONNECT AD9444 TOP VIEW (Not to Scale) Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode Rev Page DRVDD 74 DRGND DRGND 66 D0 (LSB) 65 DNC 64 DCO+ 63 DCO– 62 DRVDD 61 DRGND 60 DNC 59 DNC ...
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... D11 81 D12 84 D13 (MSB 100 DCS MODE Rev Page AD9444 Description Internal Bypass Node. Connect a 0.1 µF capacitor from this pin to AGND. Clock Input—True. Clock Input—Complement. 3.3 V Digital Output Supply (2.5V to 3.6 V). Digital Ground. Data Clock Output— Complement (CMOS Levels). ...
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... AD9444 EQUIVALENT CIRCUITS AVDD2 VIN+ AVDD2 1k Ω 2.5pF 3. Ω AVDD2 VIN– 2.5pF Figure 6. Equivalent Analog Input Circuit DRVDD 1.2V LVDSBIAS 3.74k Ω Figure 7. Equivalent LVDS BIAS Circuit V DX– V Figure 8. Equivalent LVDS Digital Output Circuit SHA DRVDD K I LVDSOUT DRVDD ...
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... Figure 15. 64K Point Single-Tone FFT/80 MSPS/100 MHz 80MSPS 125MHz @ –0.5dBFS SNR: 71.2dB ENOB: 11.6BITS SFDR: 91dBc FREQUENCY (MHz) Figure 16. 64K Point Single-Tone FFT/80 MSPS/125 MHz 80MSPS 151MHz @ –0.5dBFS SNR: 71.1dB ENOB: 11.5BITS SFDR: 87dBc FREQUENCY (MHz) Figure 17. 64K Point Single-Tone FFT/80 MSPS/151 MHz AD9444 ...
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... AD9444 75 SNR dB @ –40° SNR dB @ +25°C 72 SNR dB @ +85° 100 120 ANALOG INPUT FREQUENCY (MHz) Figure 18. SNR vs. Analog Input Frequency, 80 MSPS/LVDS Mode 105 SFDR dBc @ +85°C 100 95 SFDR dBc @ –40° 100 120 ANALOG INPUT FREQUENCY (MHz) Figure 19. SFDR vs. Analog Input Frequency, 80 MSPS/LVDS Mode 120 SECOND – ...
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... WORST THIRD-ORDER IMD (dBFS) ANALOG INPUT LEVEL (dBFS) = 9.8 MHz/10.8 MHz IN 90dBFS REFERENCE LINE SFDR (dBc) WORST THIRD-ORDER IMD (dBc) SFDR (dBFS) WORST THIRD-ORDER IMD (dBFS) ANALOG INPUT LEVEL (dBFS) = 69.3 MHz/70.3 MHz SAMPLE RATE (MSPS) = 70.3 MHz @ −0.5 dBFS IN AD9444 0 0 100 110 ...
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... AD9444 0 61.44MSPS –10 TOTAL INPUT SIGNAL POWER: –30dBFS –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 7.68 15.36 FREQUENCY (MHz) Figure 30. 64K FFT, 61.44 MSPS WCDMA 46.08 MHz 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 – ...
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... MHz Figure 39. INL Error vs. Output Code, 80 MSPS Rev Page AD9444 – TEMPERATURE (°C) Figure 38. Gain vs. Temperature 2048 4096 6144 8192 10240 12288 14336 16384 OUTPUT CODE = 15 MHz IN 80 ...
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... AD9444. Therefore, there is little advantage to the user supply- ing an external voltage reference to the AD9444. The gain trim is performed with the AD9444’s input range set p-p nominal (SENSE connected to AGND). Because of this trim, and because the 2 V p-p analog input range provides maximum ac performance, there is little benefit to using analog input ranges < ...
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... Equivalent Circuits section). Therefore, the analog source driving the AD9444 should be ac-coupled to the input pins. The recom- mended method for driving the analog input of the AD9444 is to use an RF transformer to convert single-ended signals to differential (see Figure 44). Series resistors between the output ...
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... A/D output. For that reason, considerable care was taken in the design of the clock inputs of the AD9444, and the user is advised to give careful thought to the clock source. Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and result, may be sensitive to the clock duty cycle ...
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... Note that both AVDD1 and AVDD2 must be held within 5% of the specified voltage. The DRVDD supply of the AD9444 is a dedicated supply for the digital outputs, in either LVDS or CMOS output modes. When in LVDS mode, the DRVDD should be set to 3 CMOS mode, the DRVDD supply may be connected from 2 ...
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... The evaluation boards are shipped with power supply. The evaluation boards include low dropout regulators to generate the various dc supplies required by the AD9444 and its support circuitry. Separate power supplies are provided to iso- late the DUT from the support circuitry. Each input configura- tion can be selected by proper connection of various jumpers (see Figure 47 to Figure 50 and Figure 59 to Figure 61) ...
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... AGND C40 31 0.1µF AVDD2 30 AVDD2 29 AVDD2 28 5V AVDD2 27 AVDD1 VCC 26 AVDD1 VCC C2 0.1µF OPTIONAL R28 33Ω C51 C91 10µF C3 0.1µF C9 0.1µF 0.1µF GND C24 0.1µ 3.8kΩ 3.8kΩ R3 3.8kΩ AD9444 5V GND 33Ω R35 ...
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... AD9444 ADP3338 U4 3.3V 1 GND 2 4 OUT1 OUT C57 10µF ADP3338 U3 3.3V 1 GND 2 4 OUT1 OUT C88 10µF VCC + C43 C35 C64 0.1µF 0.1µF 10µF GND VCC C10 C11 C14 GND DRVDD + C65 C47 C23 C22 10µF 0.1µF 0.1µF 0.1µ ...
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... DRO R52 PWR VDL GND GND 13 4B U10 C76 C97 C82 C80 81 10µF 0.1µF 0.1µF 0.1µF 0.1µF AD9444 220 16 ORO 15 D13O 14 D12O 13 D11O 12 D10O 11 D9O 10 D8O 9 D7O 220 16 D6O 15 D5O 14 D4O 13 D3O 12 D2O 11 D1O 10 D0O ...
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... AD9444 Figure 51. LVDS Mode Evaluation Board Layout, Primary Side Figure 52. LVDS Mode Evaluation Board Layout, Secondary Side Figure 53. LVDS Mode Evaluation Board Layout, Ground Plane 1 Figure 54. LVDS Mode Evaluation Board Layout, Ground Plane 2 Figure 55. LVDS Mode Evaluation Board Layout, Power Plane 1 Figure 56 ...
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... Figure 57. LVDS Mode Evaluation Board Layout, Primary Silkscreen Figure 58. LVDS Mode Evaluation Board Layout, Secondary Silkscreen Rev Page AD9444 ...
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... AD9444 LVDS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) Table 11. Item Qty. REFDES Description 1 1 AD9444PCB PCB, AD9444 LVDS Engineering Evaluation Board 2 16 C1, C4, C6, Capacitors, Tantalum, SMT BCAPTAJC, 10 µ 10% C33, C34, C39, C44, C55 to C57, C64, C65, C76, C87 to C89 3 38 C2, C3, C5, Capacitors, 0.1 µ ...
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... P5, P6 Power Connectors 29 1 R1, R2, R5, Resistors, Select 1/ 0402 SMD 1 R7, R13 30 1 Resistors, Select 1/ 0402 SMD R17 to R20, R27, R36 to 1 R38, R40 Select 1 Parts not placed. Manufacturer Panasonic Johnston Comp. Weiland Panasonic Panasonic Vectron Rev Page AD9444 MFG_PART_NO 142-0701-201 ...
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... AD9444 CMOS EVALUATION BOARD SCHEMATICS GND 8 VDL 7 GND 6 DRVDD 5 GND 4 VCC 3 GND MTHOLE6 H3 MTHOLE6 H2 MTHOLE6 H1 MTHOLE6 GND CR2 R39 XX C36 0.1µF C26 0.1µF 50Ω R7 50Ω R8 R37 XX R36 XX 76 D11C/D7YN D7 77 D11T/D8YN D8 78 D12C/D9YN D9 79 D12T/D10YN D10 80 D13C/D11YN D11 ...
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... OUT1 OUT 3 IN C34 + 10µF C88 + 10µF Figure 60. CMOS Mode Evaluation Board Schematic (Continued) ADP3338 U15 3.3V 1 GND 2 4 OUT1 OUT 10µF C87 + 10µF ADP3338 U14 5V 1 GND 2 4 OUT1 OUT 10µF C89 + 10µF Rev Page AD9444 P4 PJ-102A C33 + 10µF ...
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... AD9444 RZ1 220 RSO16ISO DORT/DORY DORC/D13Y XOR2IN D13T/D12Y GND D13C/D11Y D12T/D10Y VDL D12C/D9Y D11T/D8Y GND D11C/D7Y RZ2 220 RSO16ISO GND D10T/D6Y D10C/D5Y VDL D9T/D4Y D9C/D3Y GND D8T/D2Y D8C/D1Y R7 XOR2IN 7 10 D7T/D0Y RZ4 NOT PLACED 00 COUTB R50 00 COUT R16 VDL E49 E42 ...
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... Figure 63. CMOS Mode Evaluation Board Layout, Secondary Side Figure 64. CMOS Mode Evaluation Board Layout, Ground Plane 1 Figure 65. CMOS Mode Evaluation Board Layout, Ground Plane 2 Figure 66. CMOS Mode Evaluation Board Layout, Power Plane 1 Figure 67. CMOS Mode Evaluation Board Layout, Power Plane 2 Rev Page AD9444 ...
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... AD9444 Figure 68. CMOS Mode Evaluation Board Layout, Primary Silkscreen Figure 69. CMOS Mode Evaluation Board Layout, Secondary Silkscreen Rev Page ...
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... CMOS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) Table 12. Item Qty. REFDES Description 1 1 AD9444PCB PCB, AD9444 LVDS Evaluation Board 2 16 C1, C4, C6, C33, C34, Capacitors, Tantalum, SMT BCAPTAJC, 10 µ 10% C39, C44, C55 to C57, C64 to C66, C87 to C89 3 32 C2, C3, C5, C9, C12, Capacitors, 0.1 µ Ceramic X5R 0402 ...
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... AD9444 Item Qty. REFDES Description 26 26 C10, C11, C13, C14 to Capacitors, Select 10 V Ceramic X5R 0402 C19, C29, C31, C36 to C37, C38, C45, C49, C59, C62,C69, C70 to 1 C73, C90, C93, C96 Connector, Gold, Male, Coaxial, SMA, Vertical 28 15 R1,R2,R5,R7, R13, ...
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... SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. 3. THE EXPOSED HEAT SINK SOLDERED TO THE GROUND PLANE IS REQUIRED FOR THE 100-LEAD TQFP/EP. ORDERING GUIDE Model Temperature Range 1 AD9444BSVZ-80 –40°C to +85°C AD9444-CMOS/PCB AD9444-LVDS/PCB Pb-free part. 16.00 SQ 14.00 SQ 100 TOP VIEW ...
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... AD9444 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05089–0–10/04(0) Rev Page ...