AD9985A/PCB Analog Devices Inc, AD9985A/PCB Datasheet

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AD9985A/PCB

Manufacturer Part Number
AD9985A/PCB
Description
KIT EVAL FOR AD9985A
Manufacturer
Analog Devices Inc
Series
Advantiv®r
Type
Video Processorr
Datasheet

Specifications of AD9985A/PCB

Contents
Evaluation Board
For Use With/related Products
AD9985A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FEATURES
Variable analog input bandwidth control
Variable SOGIN bandwidth control
Automated clamping level adjustment
140 MSPS maximum conversion rate
300 MHz analog bandwidth
0.5 V to 1.0 V analog input range
500 ps p-p PLL clock jitter at 110 MSPS
3.3 V power supply
Full sync processing
Selectable input filtering
Sync detect for hot plugging
Midscale clamping
Power-down mode
Low power: 500 mW typical
4:2:2 output format mode
APPLICATIONS
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TVs
GENERAL DESCRIPTION
The AD9985A is a complete 8-bit, 140 MSPS, monolithic
analog interface optimized for capturing RGB graphics signals
from personal computers and workstations. Its 140 MSPS
encode rate capability and full power analog bandwidth of 300
MHz support resolutions up to SXGA (1280 × 1024 at 75 Hz).
The AD9985A includes a 140 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and horizontal sync (Hsync) and Coast signals.
Three-state CMOS outputs can be powered from 2.5 V to 3.3 V.
The AD9985A’s on-chip PLL generates a pixel clock from the
Hsync input. Pixel clock output frequencies range from 12 MHz
to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Analog Interface for Flat Panel Displays
When the Coast signal is presented, the PLL maintains its
output frequency in the absence of Hsync. A sampling phase
adjustment is provided. Data, Hsync, and clock output phase
relationships are maintained. The AD9985A also offers full sync
processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or can be provided by the
user through the CLAMP input pin. This interface is fully
programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9985A is
provided in a space-saving 80-lead LQFP surface-mount
Pb-free plastic package, and is specified over the –40°C to
+85°C temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
CLAMP
HSYNC
COAST
SOGIN
FILT
SDA
SCL
R
G
B
A0
IN
IN
IN
FUNCTIONAL BLOCK DIAGRAM
CLAMP
CLAMP
CLAMP
SERIAL REGISTER AND
POWER MANAGEMENT
PROCESSING
GENERATION
AND CLOCK
LEVEL ADJUST
LEVEL ADJUST
LEVEL ADJUST
© 2005 Analog Devices, Inc. All rights reserved.
AUTO-CLAMP
AUTO-CLAMP
AUTO-CLAMP
SYNC
110 MSPS/140 MSPS
Figure 1.
A/D
A/D
A/D
AD9985A
REF
8
8
8
AD9985A
www.analog.com
R
G
B
MIDSCV
DTACK
HSOUT
VSOUT
SOGOUT
REF
BYPASS
OUTA
OUTA
OUTA

Related parts for AD9985A/PCB

AD9985A/PCB Summary of contents

Page 1

FEATURES Variable analog input bandwidth control Variable SOGIN bandwidth control Automated clamping level adjustment 140 MSPS maximum conversion rate 300 MHz analog bandwidth 0 1.0 V analog input range 500 ps p-p PLL clock jitter at 110 MSPS ...

Page 2

AD9985A TABLE OF CONTENTS Specifications..................................................................................... 3 Explanation of Test Levels ........................................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Design Guide................................................................................... 11 General Description................................................................... 11 Digital Inputs .............................................................................. 11 Input Signal Handling................................................................ 11 Hsync, ...

Page 3

SPECIFICATIONS 3.3 V, ADC clock = maximum conversion rate, unless otherwise noted Table 1. Parameter Temp RESOLUTION DC ACCURACY Differential Nonlinearity 25°C Full Integral Nonlinearity 25°C Full No Missing Codes Full ANALOG ...

Page 4

AD9985A Parameter Temp DIGITAL OUTPUTS Output Voltage, High (V ) Full OH Output Voltage, Low (V ) Full OL Duty Cycle DATACK Full Output Coding POWER SUPPLY V Supply Voltage Full D V Supply Voltage Full DD P Supply Voltage ...

Page 5

3.3 V, ADC clock = maximum conversion rate, unless otherwise noted Table 2. Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity ANALOG INPUT Input Voltage Range Minimum Maximum Gain Tempco Input Bias ...

Page 6

AD9985A Parameter POWER SUPPLY V Supply Voltage D V Supply Voltage DD P Supply Voltage VD I Supply Current ( Supply Current ( Supply Current ( Total Power ...

Page 7

ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Analog Inputs Digital Inputs Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 ...

Page 8

AD9985A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 GND GREEN <7> 2 GREEN <6> 3 GREEN <5> 4 GREEN <4> 5 GREEN <3> 6 GREEN <2> 7 GREEN <1> 8 GREEN <0> 9 GND BLUE <7> 12 ...

Page 9

Pin Type Mnemonic Function Power Supply V Analog Power Supply D V Output Power Supply DD PV PLL Power Supply D GND Ground Serial Port (2-Wire) SDA Serial Port Data I/O SCL Serial Port Data Clock (100 kHz maximum) A0 ...

Page 10

AD9985A Pin Description Data Outputs RED Data Output, Red Channel. GREEN Data Output, Green Channel. BLUE Data Output, Blue Channel. The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed. When ...

Page 11

DESIGN GUIDE GENERAL DESCRIPTION The AD9985A is a fully integrated solution for capturing analog RGB signals and digitizing them for display on flat panel moni- tors or projectors. The circuit is ideal for providing a computer interface for HDTV monitors ...

Page 12

AD9985A black output (code 0x00) when the known black input is present. The offset then remains in place when other signal levels are processed, and the entire signal is shifted to eliminate offset errors. In most PC graphics systems, black ...

Page 13

ADC during the back porch of the input signals, the AD9985A can self-adjust to eliminate any offset errors in its own ADC channels, as well as any offset errors present on the incoming graphics or video ...

Page 14

AD9985A 100 110 120 130 140 150 FREQUENCY (MHz) Figure 7. Pixel Clock Jitter vs. Frequency The PLL characteristics are determined by ...

Page 15

Table 9. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats Standard Refresh Modes Resolution Rate VGA 640 × 480 SVGA 800 × 600 ...

Page 16

AD9985A COAST TIMING In most computer systems, the Hsync signal is provided continuously on a dedicated wire. In these systems, the Coast input and function are unnecessary and should not be used, and the pin should be permanently connected to ...

Page 17

SERIAL REGISTER MAP The AD9985A is initialized and controlled by a set of registers that determine the operating modes. An external controller is used to write and read the control registers through the two-line serial interface port. Table 10. ...

Page 18

AD9985A Write and Hexadecimal Read or Default Address Read-Only Bits Value *1****** **0***** ***0**** ****1*** *****1** ******1* 0x10 R/W 7:3 10111*** *****0** ******0* *******0 0x11 R/W 7:0 00100000 0x12 R/W 7:0 00000000 0x13 R/W 7:0 00000000 0x14 RO 7:0 0x15 ...

Page 19

Write and Hexadecimal Read or Default Address Read-Only Bits Value 0x16 R/W 7 0******* 6:5 *00***** 4 ***0**** 3:0 ****0000 0x17 RO 7:0 0x18 RO 7:0 0x19 R/W 7:0 00000100 0x1A R/W 7:0 00000100 0x1B R/W 7:0 00000100 0x1C 7:0 ...

Page 20

AD9985A The power-up default value of PLLDIV is 1693 (PLLDIVM = 0x69, PLLDIVL = 0xDx). The AD9985A updates the full divide ratio only when this register is written to. CLOCK GENERATOR CONTROL 03 7–6 VCO Range Select Two bits that ...

Page 21

Green Channel Gain Adjust (GREENGAIN) An 8-bit word that sets the gain of the green channel. See REDGAIN (08). 0A 7–0 Blue Channel Gain Adjust (BLUEGAIN) An 8-bit word that sets the gain of the blue channel. See ...

Page 22

AD9985A Table 16. Active Hsync Override Settings Override Result 0 Autodetermines the active interface (power-up default) 1 Override, Bit 3 determines the active interface 0E 3 Active Hsync Select This bit is used under two conditions used to ...

Page 23

Table 24. Coast Input Polarity Override Settings Override Result 0 Determined by chip (power-up default) 1 Determined by user 0F 3 Coast Input Polarity This bit indicates the polarity of the Coast signal that is applied to the PLL COAST ...

Page 24

AD9985A 14 7 Hsync Detect This bit is used to indicate when activity is detected on the Hsync input pin (Pin 30). If Hsync is held high or low, activity will not be detected. Table 31. Hsync Detection Results Detect ...

Page 25

Table 38. Detected Coast Input Polarity Status Polarity Status Result 0 Coast polarity negative 1 Coast polarity positive This indicates that Bit 1 of Register 5 is the 4:2:2 output mode select bit 4:2:2 Output Mode Select A ...

Page 26

AD9985A 2-WIRE SERIAL CONTROL PORT A 2-wire serial interface control interface is provided. Two AD9985A devices can be connected to the 2-wire serial interface; each device has a unique address. The 2-wire serial interface comprises a clock (SCL) and a ...

Page 27

Serial Interface Read/Write Examples Write to one control register: 1. Start signal 2. Slave address byte (R/ W Bit = low) 3. Base address byte 4. Data byte to base address 5. Stop signal Write to four consecutive control registers: ...

Page 28

AD9985A Table 46. Control of the Sync Block Muxes via the Serial Register Mux No. Serial Bus Control Bit 1 and 2 0x0E: Bit 3 3 0x0F: Bit 5 4 0x0E: Bit 0 SYNC SLICER The purpose of the sync ...

Page 29

PCB LAYOUT RECOMMENDATIONS The AD9985A is a high precision, high speed analog device. Consequently, to get the maximum performance out of the part important to have a board with a good layout. This section provides guidelines for designing ...

Page 30

AD9985A OUTPUTS (BOTH DATA AND CLOCKS) Try to minimize the trace length that the digital outputs have to drive. Longer traces have higher capacitance, which requires more current, which causes more internal digital noise. Shorter traces reduce the possibility of ...

Page 31

... OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model 1 AD9985ABSTZ-110 1 AD9985AKSTZ-110 AD9985AKSTZ-140 1 AD9985A/PCB Pb-free part. 16.20 16.00 SQ 0.75 1.60 15.80 0.60 MAX 0. PIN 1 TOP VIEW (PINS DOWN) 0.20 0.09 7° 3.5° 20 0° ...

Page 32

AD9985A NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05484-0-7/05(0) Rev Page ...

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