ADIS16201/EVAL Analog Devices Inc, ADIS16201/EVAL Datasheet - Page 26

• Manufacturer Part Number: ADIS16201/EVAL
• Description: BOARD EVAL ADIS16201 W/SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of ADIS16201/EVAL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADIS16201
Table 28. COMMAND Bit Descriptions
Bit
15:8
7
6:4
3
2
1
0
MISCELLANEOUS CONTROL REGISTER
The MSC_CTRL control register within the ADIS16201
provides control of two miscellaneous functions: the data-ready
hardware I/O function and the self-test function. The bits to
control these two functions are shown in Table 29.
The operation of the data-ready hardware I/O function is very
similar to the alarm hardware I/O function (controlled through
the ALM_CTRL control register). In this case, the MSC_CNTRL
register can be used in setting up one of the two GPIO pins to
serve as the hardware output pin that indicates when the
sampling, conversion, and processing of the seven data output
variables has been completed. This register provides the ability
to enable the data-ready hardware function and establish its
polarity.
Description
Not used.
Software Reset Command. Allows for resetting of the
device via the SPI.
Not used.
Manual Flash Update Command. This command is
utilized in updating all of the nonvolatile registers to
flash. Once the command is initiated, the supply
voltage, VDD, must remain within specified limits for
50 ms to assure proper update of the nonvolatile
registers to flash.
Auxiliary DAC Latch Command. This command acts to
latch the AUX_DAC control register data into the
auxiliary DAC upon receipt of the command. This allows
for sequential loading of the upper and lower AUX_DAC
data bytes via the SPI without having the auxiliary DAC
transition into unwanted, intermediate states based
upon the individual AUX_DAC data bytes. Once the two
bytes of AUX_DAC are loaded, the DAC latch command
is initiated to move the data into the auxiliary DAC itself.
Factory Reset Command. Allows the user to reset all
four system level offset registers and all four system
level scale registers to the nominal settings (000h and
800h, respectively) upon receipt of command. Data
within the moving average filters will likewise be reset.
As the manual flash command identified below, this
command stores all of the nonvolatile registers to flash.
Once the command is initiated, the supply voltage, VDD,
must remain within specified limits for 50 ms to assure
proper update of the nonvolatile registers to flash.
Null Command. Loads the X/Y inclination offset as well
as the X/Y acceleration offset registers with values that
zero out the inclination and acceleration outputs.
Useful as a single command to simultaneously zero
both inclination and acceleration outputs. As the
manual flash command identified below, this command
stores all of the nonvolatile registers to flash. Once the
command is initiated, the supply voltage, VDD, must
remain within specified limits for 50 ms to assure
proper update of the nonvolatile registers to flash.
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The data-ready hardware I/O pin is reset automatically to an
inactive state part way through the next conversion cycle,
resulting in a pulse train with a duty cycle varying from ~15%
to 35%, depending upon the sample period setting. Upon
completion of the next sample/conversion/processing cycle, the
data ready hardware I/O line is reasserted.
The MSC_CTRL, ALM_CTRL, and GPIO_CTRL control
registers can influence the same GPIO pins. A priority level has
been established to avoid conflicting assignments of the two
GPIO pins. This priority level is defined as MSC_CTRL and has
precedence over ALM_CTRL, which has precedence over
GPIO_CTRL.
The self-test enable bit allows the user to place the ADIS16201
into a diagnostics mode for purposes of verifying the base
sensor’s operation. When this bit is set high, an electrostatic
force is generated internally to the sensor. The resulting
movement within the sensor allows the end user to test if the
accelerometer is functional. Typical change in the output is
328 m g (corresponding to 708 LSB). Once the self-test enable
bit is returned to a low state, normal operation is resumed.
MSC_CTRL Register Definition
Address
0x35, 0x34
1
The 16-bit miscellaneous control register is used in the
controlling of the self-test and data-ready hardware functions.
This includes turning on and off the self-test function, as well as
enabling and configuring the data-ready function. For the data-
ready function, the written values are nonvolatile, allowing for
data recovery upon reset. The self-test data is volatile and is set
to 0s upon reset. This register has read/write capability.
Table 29. MSC_CTRL Bit Descriptions
Bit
15:9
8
7:3
2
1
0
Default is valid only until the first register write cycle.
Description
Not used.
Self-test enable.
Not used.
Data-ready enable.
Data-ready polarity.
Data-ready line select.
1: DR enabled
0: DR disabled
1: DIO1
0: DIO0
1: ST enabled
0: ST disabled
1: Active high
0: Active low
Default
0x0000
1
Format
N/A
Access
R/W