AD9704-EB Analog Devices Inc, AD9704-EB Datasheet
AD9704-EB
Specifications of AD9704-EB
Related parts for AD9704-EB
AD9704-EB Summary of contents
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... Easy Interfacing to Other Components. Adjustable common-mode output allows for easy interfacing to other signal chain components that accept common-mode levels from 1 On-Chip Voltage Reference. The AD9704/AD9705/AD9706/ AD9707 include a 1.0 V temperature-compensated band gap voltage reference. 9. Industry-Standard 32-Lead LFCSP_VQ Package. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...
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... Absolute Maximum Ratings.......................................................... 10 Thermal Characteristics ............................................................ 10 Pin Configurations and Function Descriptions ......................... 11 AD9707 ........................................................................................ 11 AD9706 ........................................................................................ 12 AD9705 ........................................................................................ 13 AD9704 ........................................................................................ 14 Typical Performance Characteristics ........................................... 15 AD9707 ........................................................................................ 15 AD9704, AD9705, and AD9706............................................... 22 Terminology .................................................................................... 28 Theory of Operation ...................................................................... 29 REVISION HISTORY 4/07—Rev. 0: Rev. A Changes to Features List .................................................................. 1 Changes to Product Highlights....................................................... 1 Changes to General Description .................................................... 3 Changes to Table 3............................................................................ 6 Changes to Table 4 ...
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... In addition, a power- down mode reduces the standby power dissipation to approxi- mately 2.2 mW. The AD9704/AD9705/AD9706/AD9707 has an optional serial peripheral interface (SPI®) that provides a higher level of program- mability to enhance performance of the DAC. An adjustable output, common-mode feature allows for easy interfacing to other components that require common modes from ...
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... Rev Page AD9705 AD9704 Min Typ Max Min Typ Max 10 8 ±0.10 ±0.36 ±0.03 ±0.10 ±0.09 ±0.31 ±0.02 ±0.03 −0.03 0 +0.03 −0.03 0 +0.03 − ...
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... Rev Page AD9704/AD9705/AD9706/AD9707 AD9705 AD9704 Min Typ Max Min Typ 0.6 1 0.6 42.5 58 42.5 −0.2 +0.03 +0.2 −0.2 +0.03 −40 +85 −40 AD9705 AD9704 Min Typ Max Min Typ 175 175 2.5 2.5 2.5 2 ...
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... Max 3 2 0.9 0 0.9 +10 −10 + 1.4 0.3 1.6 0.6 2 1.5 2.25 0.75 1.5 2.25 1.5 0.5 1.5 Rev Page AD9705 AD9704 Min Typ Max Min Typ 2 0.9 0 −10 +10 − 1.4 1.4 0.3 0.3 1.6 1.6 0.6 0.6 2.8 2 0.75 1 ...
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... Rev Page AD9704/AD9705/AD9706/AD9707 AD9705 AD9704 Min Typ Max Min Typ 10 8 ±0.10 ±0.36 ±0.03 ±0.09 ±0.30 ±0.02 −0.03 0 +0.03 −0.03 0 −2.7 −0.2 +2.7 −2.7 −0.2 ...
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... Rev Page AD9705 AD9704 Min Typ Max Min Typ 0.22 0.28 0.22 9.5 16 9.5 −1 −0.1 +1 −1 −0.1 −40 +85 −40 AD9705 AD9704 Min Typ Max Min Typ 5.6 5 2.5 2.5 2.5 2 −135.1 −126.3 9.5 8.0 ...
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... LPW IOUTA OR IOUTB 0.1% Figure 2. Timing Diagram Rev Page AD9704/AD9705/AD9706/AD9707 AD9705 AD9704 Min Typ Max Min Typ 1.2 1.8 1.2 1 +10 10 − − + 2.3 2 2.4 2.4 0.1 0.1 6.2 6 ...
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... AD9704/AD9705/AD9706/AD9707 ABSOLUTE MAXIMUM RATINGS Table 7. With Parameter Respect to AVDD ACOM DVDD DCOM CLKVDD CLKCOM ACOM DCOM ACOM CLKCOM DCOM CLKCOM AVDD DVDD AVDD CLKVDD DVDD CLKVDD SLEEP DCOM Digital Inputs, MODE DCOM IOUTA, IOUTB ACOM REFIO, FS ADJ, OTCM ACOM CLK+, CLK–, CMODE ...
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... CLKCOM Clock Common. 13 CLK− Negative Differential Clock Input. 12 CLK+ Positive Differential Clock Input. 11 CLKVDD Clock Supply Voltage (1 3.6 V). 10, 26 DCOM Digital Common. 3 DVDD Digital Supply Voltage (1 3.6 V). AD9704/AD9705/AD9706/AD9707 DB7 ADJ PIN 1 DB6 2 23 REFIO INDICATOR DVDD 3 22 ACOM AD9707 DB5 ...
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... AD9704/AD9705/AD9706/AD9707 AD9706 Table 10. AD9706 Pin Function Descriptions Pin No. Mnemonic Description 27 DB11 (MSB) Most Significant Data Bit (MSB 32, DB10 to DB1 Data Bit 10 to Data Bit DB0 (LSB) Least Significant Data Bit (LSB). 25 SLEEP/CSB In pin mode, active high powers down chip. In SPI mode, this pin is the serial port chip select (active low). ...
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... DCOM Digital Common Connect. 3 DVDD Digital Supply Voltage (1 3.6 V). DB3 ADJ PIN 1 DB2 2 23 REFIO INDICATOR DVDD 3 22 ACOM AD9705 DB1 4 21 IOUTA DB0 (LSB IOUTB TOP VIEW OTCM (Not to Scale AVDD PIN/SPI/RESET CONNECT Figure 5. AD9705 Pin Configuration Rev Page AD9704/AD9705/AD9706/AD9707 ...
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... AD9704/AD9705/AD9706/AD9707 AD9704 Table 12. AD9704 Pin Function Descriptions Pin No. Mnemonic Description 27 DB7 (MSB) Most Significant Data Bit (MSB 32, 1 DB6 to DB1 Data Bit 6 to Data Bit 1. 2 DB0 (LSB) Least Significant Data Bit (LSB). 25 SLEEP/CSB In pin mode, active high powers down chip. ...
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... OUT Figure 9. SFDR vs MSPS OUT 100 Rev Page AD9704/AD9705/AD9706/AD9707 (MHz) OUT Figure 10. SFDR vs 125 MSPS OUT (MHz) OUT Figure 11. SFDR vs 175 MSPS OUT I = 5mA OUTFS I = 2mA OUTFS I = 1mA OUTFS (MHz) OUT Figure 12. SFDR vs. f and I @ 175 MSPS OUT OUTFS 55 60 ...
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... AD9704/AD9705/AD9706/AD9707 OTCM = OTCM = 1. (MHz) OUT Figure 13. SFDR vs. f and OTCM @ 175 MSPS OUT 65MSPS CLOCK –10 –8 –6 –4 A (dBFS) OUT Figure 14. SFDR vs. A and f OUT CLOCK –115 –120 –125 f = 125MSPS CLOCK –130 f = 65MSPS CLOCK –135 –140 –145 –150 –155 –160 ...
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... CODE Figure 20. Typical Uncalibrated DNL 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 5000 10000 CODE Figure 21. Typical Calibrated INL AD9704/AD9705/AD9706/AD9707 0.6 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 0 15000 +25° 15000 Figure 23. SFDR vs. f – ...
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... AD9704/AD9705/AD9706/AD9707 –10 f – –30 SFDR = 74dBc AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) Figure 25. Dual-Tone SFDR = 78MSPS CLOCK = 15.0MHz OUT1 = 15.4MHz OUT2 Rev Page – 78MSPS CLOCK – 15.0MHz OUT1 f = 15.4MHz OUT2 – 15.8MHz OUT3 f = 16.2MHz OUT4 – ...
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... OUT Figure 27. SFDR vs (MHz) OUT Figure 28. SFDR vs MSPS OUT (MHz) OUT Figure 29. SFDR vs MSPS OUT 100 OUT Rev Page AD9704/AD9705/AD9706/AD9707 1mA OUTFS 2mA OUTFS (MHz) OUT Figure 30. SFDR vs. f and MSPS OUT OUTFS 1mA 75 OUTFS 2mA OUTFS (MHz) OUT Figure 31. SFDR vs. f ...
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... AD9704/AD9705/AD9706/AD9707 –115 –120 –125 –130 f = 65MSPS, CLOCK I = 1mA OUTFS –135 –140 –145 f = 65MSPS, CLOCK I = 2mA –150 OUTFS –155 –160 (dBFS) OUT Figure 33. NSD vs and I OUT CLOCK CLOCK 25MSPS CLOCK LOWER (MHz) OUT Figure 34. Dual-Tone IMD vs. Lower OUT CLOCK f = 25MSPS 70 CLOCK 65 60 ...
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... OUT SFDR = 80dBc 31 36 Rev Page AD9704/AD9705/AD9706/AD9707 f = 78MSPS CLOCK f = 15.0MHz OUT1 f = 15.4MHz OUT2 SFDR = 77dBc AMPLITUDE = 0dBFS FREQUENCY (MHz) Figure 42. Dual-Tone SFDR f = 78MSPS CLOCK f = 15.0MHz OUT1 ...
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... AD9705 –135 –140 –145 AD9706 –150 AD9707 –155 –160 (MHz) OUT Figure 44. AD9704, AD9705, AD9706, AD9707 NSD vs. f 175 MSPS 0.03 0.02 0.01 0 –0.01 –0. 100 150 CODE Figure 45. AD9704 Typical Uncalibrated INL 0.01 0 –0.01 –0.02 –0. 100 ...
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... OUT SFDR = 67dBc –30 AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) Figure 51. AD9704 Single-Tone SFDR – 78MSPS CLOCK – 15.0MHz OUT1 f = 15.4MHz OUT2 –30 SFDR = 67dBc AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 – ...
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... AD9704/AD9705/AD9706/AD9707 –10 f – –30 SFDR = 77dBc AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) Figure 56. AD9706 Dual-Tone SFDR = 78MSPS CLOCK = 15.0MHz OUT1 = 15.4MHz OUT2 Rev Page ...
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... AD9704 –125 –130 AD9705 –135 –140 –145 AD9706 AD9707 –150 –155 –160 (MHz) OUT Figure 57. AD9704, AD9705, AD9706, AD9707 NSD vs. f 0.04 0.03 0.02 0.01 0 –0.01 –0. 100 150 CODE Figure 58. AD9704 Typical Uncalibrated INL 0.01 0 –0.01 –0.02 –0. 100 ...
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... Figure 64. AD9704 Single-Tone SFDR –10 f – –30 SFDR = 67dBc AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) Figure 65. AD9704 Dual-Tone SFDR 3000 4000 = 78MSPS CLOCK = 15.0MHz OUT 78MSPS CLOCK = 15.0MHz OUT1 = 15.4MHz OUT2 Rev Page – 78MSPS CLOCK – ...
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... CLOCK – 15.0MHz OUT1 f = 15.4MHz OUT2 –30 SFDR = 73dBc AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) Figure 69. AD9706 Dual-Tone SFDR AD9704/AD9705/AD9706/AD9707 31 36 Rev Page ...
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... AD9704/AD9705/AD9706/AD9707 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. ...
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... The interface allows read/write access to all registers that configure the AD9704/AD9705/AD9706/AD9707. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The serial interface port of the AD9704/AD9705/AD9706/ AD9707 is configured as a single pin I/O. General Operation of the Serial Interface There are two phases to a communication cycle with the AD9704/AD9705/AD9706/AD9707 ...
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... The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9704/ AD9705/AD9706/AD9707 and the system controller. Phase 2 of the communication cycle is a transfer of one, two, three, or four data bytes, as determined by the instruction byte ...
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... N N Bit 5 Bit 4 Bit 3 SWRST LNGINS PDN DCLKPOL DESKEW VER[3] CALMEM[1] CALMEM[0] SMEMWR MEMADDR[5] MEMADDR[4] MEMADDR[3] MEMDATA[5] MEMDATA[4] MEMDATA[3] CALDACFS Rev Page AD9704/AD9705/AD9706/AD9707 INSTRUCTION CYCLE DATA TRANSFER CYCLE R Figure 75. Serial Register Interface Timing, LSB First Read SCLK t t PWH PWL t DS ...
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... AD9704/AD9705/AD9706/AD9707 SPI REGISTER DESCRIPTIONS Table 16. SPI CTL—Register 0x00 Mnemonic Bit No. Direction (I/O) SDIODIR 7 I DATADIR 6 I SWRST 5 I LNGINS 4 I PDN 3 I SLEEP 2 I CLKOFF 1 I EXREF 0 I Table 17. DATA—Register 0x02 Mnemonic Bit No. Direction (I/O) DATAFMT 7 I DCLKPOL 4 I DESKEW ...
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... Bit No. Direction (I/O) MEMDATA[5:0] [5:0] I/O Table 23. TRIM—Register 0x14 Mnemonic Bit No. Direction (I/O) CALDACFS 4 I AD9704/AD9705/AD9706/AD9707 Default Description 0 1: Calibration cycle complete Initiate device self-calibration Write to static memory (calibration coefficients Read from static memory (calibration coefficients Reset calibration coefficients to default (uncalibrated). ...
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... The control amplifier allows a 5:1 adjustment span of I from setting I 156.25 μA (R span the power dissipation of the AD9704/AD9705/AD9706/ AD9707, which is proportional to I section). The second benefit relates to the ability to adjust the output over range, which is useful for controlling the transmitted power. ...
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... ACOM via Pin 19 (OTCM). This extends the compliance range of the outputs and facilitates interfacing the output of the AD9704/ AD9705/AD9706/AD9707 to components that require common- mode levels other than 0 V. The OTCM pin demands dynami- ...
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... The AD9704/AD9705/AD9706/ AD9707 are rising-edge triggered and so exhibits dynamic performance sensitivity when the data transition is close to this edge. In general, the goal when applying the AD9704/ AD9705/AD9706/AD9707 is to make the data transition close to the falling clock edge. This becomes more important as the sample rate increases ...
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... CLOCK 75MSPS CLOCK 25MSPS CLOCK 10MSPS CLOCK 0 0.01 0 OUT CLOCK Figure 83 Ratio @ DVDD = 3.3 V DVDD OUT CLOCK AD9704/AD9705/AD9706/AD9707 2.5 2.5 2.0 1.5 1.0 0 0.01 Figure 84. I DVDD 2.00 0 Figure 85. I 1.4 1.2 1.0 0.8 0.6 0.4 0 Figure 86. I vs. f CLKVDD CLOCK Rev ...
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... Logic 1 to the SLEEP/CSB pin. The SLEEP/CSB pin logic threshold is equal to 0.5 × DVDD. This digital input also contains an active pull-down circuit. The AD9704/AD9705/AD9706/AD9707 take less than power down and approximately 5 μs to power back up. Sleep and Power-Down Operation (SPI Mode) The AD9704/AD9705/AD9706/AD9707 offer three power- down functions that can be controlled through the SPI ...
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... Register 0x0F. 6. Disable the calibration clock by clearing the CALCLK Bit (Register 0x02, Bit 0). The AD9704/AD9705/AD9706/AD9707 devices allow reading and writing of the calibration coefficients. There are 33 coefficients in total. The read/write feature of the coefficients can be useful for improving the results of the self-calibration routine by averaging the results of several calibration results and loading the aver- aged results back into the device ...
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... VSWR. Note that approxi- mately half the signal power is dissipated across R SINGLE-ENDED BUFFERED OUTPUT USING AN OP AMP An op amp such as the ADA4899-1 can be used to perform a single-ended current-to-voltage conversion, as shown in Figure 90. The AD9704/AD9705/AD9706/AD9707 are config- ured with a pair of series resistors, R feedback resistor, R formula V OUT ...
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... ⎜ ⎟ MAX REF ⎝ R ⎠ − V MIN MAX OUT The common-mode voltage of the output is determined by the formula V = − OUT MAX 2 AD9704/AD9705/AD9706/AD9707 AD9704/AD9705 AD9706/AD9707 IOUTA 21 REFIO 23 OTCM IOUTB 20 Figure 91. Single-Supply Differential Buffer Rev Page – ADA4841 OUT + ADA4841-2 – ...
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... The digital inputs are designed to be driven from various data pattern generators, with the on-board option to add a resistor network for proper load termination. Provisions are also made to operate the AD9704/AD9705/AD9706/AD9707 with either the internal or the external reference exercise the power- down feature. ...
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... EVALUATION BOARD SCHEMATICS RIBBON R A Figure 92. Digital Inputs Rev Page AD9704/AD9705/AD9706/AD9707 05926-051 RCOM ...
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... AD9704/AD9705/AD9706/AD9707 3 RC060 3 RC060 3 RC060 3 RC060 Figure 93. Output Signal Conditioning Rev Page 05926-052 3 RC060 RC080 5 JP9 ERA6YEB323V,ERA6Y RC080 5 JP8 ERA6YEB323V,ERA6Y RC080 5 JP7 ERA6YEB323V,ERA6Y 3 RC060 R7 ...
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... RC0603 JP20 JP23 CC0603 JP30 JP21 Figure 94. Clock Rev Page AD9704/AD9705/AD9706/AD9707 05926-053 RC0603 CC0603 JP16 ...
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... AD9704/AD9705/AD9706/AD9707 3 RC060 JP5 3 RC060 JP4 JP1 3 RC060 Figure 95. SPI Rev Page 05926-054 ...
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... RC0603 RC0603 CC0603 CC0603 Figure 96. Power Supplies Rev Page AD9704/AD9705/AD9706/AD9707 05926-077 RC0603 RC0603 CC0603 CC0603 ...
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... AD9704/AD9705/AD9706/AD9707 EVALUATION BOARD LAYOUT Figure 97. Assembly—Primary Side Figure 98. Assembly—Secondary Side Rev Page ...
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... AD9704/AD9705/AD9706/AD9707 Figure 99. Layer 1—Primary Side Figure 100. Layer 4—Secondary Side Rev Page ...
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... AD9704/AD9705/AD9706/AD9707 Figure 101. Layer 2—Ground Plane Figure 102. Layer 3—Power Plane Rev Page ...
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... AD9705BCPZRL7 −40°C to +85°C AD9706BCPZ 1 −40°C to +85°C 1 AD9706BCPZRL7 −40°C to +85°C AD9707BCPZ 1 −40°C to +85°C 1 AD9707BCPZRL7 −40°C to +85°C AD9704-EB AD9705-EB AD9706-EB AD9707- RoHS Compliant Part. 5.00 BSC SQ 0.60 MAX 0.50 BSC TOP 4.75 VIEW BSC SQ 0 ...
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... AD9704/AD9705/AD9706/AD9707 NOTES ©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05926-0-4/07(A) Rev Page ...