CY3682 Cypress Semiconductor Corp, CY3682 Datasheet
CY3682
Specifications of CY3682
CY3682
Related parts for CY3682
CY3682 Summary of contents
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... SSOP and QFN Package ■ Complies with most Device Class Specifications ■ 3. Logic Block Diagram 24 MHz XTAL DPLUS DMINUS Cypress Semiconductor Corporation Document #: 38-08013 Rev. *J EZ-USB SX2™ High Speed USB 2. Applications DSL modems ■ ATA interface ■ Memory card readers ■ ...
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Introduction The EZ-USB SX2™ USB interface device is designed to work with any external master, such as standard microprocessors, DSPs, ASICs, and FPGAs to enable USB 2.0 support for any peripheral design. SX2 has a built in USB transceiver ...
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IFCONFIG: The IFCONFIG byte contains the settings for the ■ IFCONFIG register. The IFCONFIG register bits are defined in IFCONFIG Register 0x01 on page 17. If the external master requires an interface configuration different from the default, that interface can ...
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Bit 6: EP0BUF If this interrupt is enabled, and the Endpoint 0 buffer becomes available to the external master for read or write operations, the SX2 asserts the INT# pin and sets bit 6 in the Interrupt Status Byte. This ...
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Figure 5-1. Endpoint Configurations (High Speed Mode & ...
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The SX2 accepts either an internally derived clock (30 MHz or 48 MHz) or externally supplied clock (IFCLK MHz), and SLRD, SLWR, SLOE, PKTEND, CS#, FIFOADR[2:0] signals from an external master. The interface can be selected for ...
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Command Protocol An address FIFOADR [2:0] selects the command interface. The command interface is used to write to and read from the SX2 registers and the Endpoint 0 buffer, as well as the descriptor ...
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Enumeration The SX2 has two modes of enumeration. The first mode is automatic through EEPROM boot load, as described in Methods on page 2. The second method is a manual load of the descriptor or VID, PID, and DID ...
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To send more than 64 bytes, the process is repeated. The SX2 internally stores the length of the data phase that was specified in the wLength field (bytes 6,7) of the setup packet. To send less than the requested amount ...
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A two-step process is employed to clear an endpoint data toggle bit to 0. First, write to the TOGCTL register with an endpoint address (EP3:EP0) plus a direction bit (IO). Keeping the endpoint and direction bits the same, write a ...
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Pin Configurations Figure 8-1. CY7C68001 56-Pin SSOP Pin Assignment Note denotes programmable polarity. Document #: 38-08013 Rev. *J FD13 FD12 1 FD14 FD11 2 FD15 FD10 3 GND FD9 4 NC FD8 5 VCC *WAKEUP 6 ...
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Figure 8-2. CY7C68001 56-pin QFN Assignment * SLRD 1 * SLW R 2 AVCC 3 XTALOUT 4 XTALIN 5 AGND 6 VCC 7 DPLUS 8 DMINUS 9 GND 10 VCC 11 GND 12 * IFCLK 13 RESERVED 14 Document #: ...
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CY7C68001 Pin Definitions Table 8-1. SX2 Pin Definitions QFN SSOP Name Type Default Pin Pin 3 10 AVCC Power N AGND Power N DMINUS I/O DPLUS I/O RESET# Input N/A 5 ...
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Table 8-1. SX2 Pin Definitions (continued) QFN SSOP Name Type Default Pin Pin 52 3 FD[15] I/O SLRD Input N SLWR Input N FLAGA Output 30 37 FLAGB Output 31 38 FLAGC Output 13 ...
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Register Summary Table 9-1. SX2 Register Summary Hex Size Name Description General Configuration 01 1 IFCONFIG Interface Configuration 02 1 FLAGSAB FIFO FLAGA and FLAGB Assignments 03 1 FLAGSCD FIFO FLAGC and FLAGD Assignments 04 1 POLAR FIFO polarities ...
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Table 9-1. SX2 Register Summary (continued) Hex Size Name Description 2E 1 INTENABLE Interrupt Enable Descriptor 30 500 DESC Descriptor RAM Endpoint EP0BUF Endpoint 0 Buffer 32 8/1 SETUP Endpoint 0 Setup Data / Stall 33 1 ...
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IFCONFIG Register 0x01 IFCONFIG Bit # 7 6 Bit Name IFCLKSRC 3048 MHZ Read/Write R/W R/W Default 1 1 9.1.1 Bit 7: IFCLKSRC This bit selects the clock source for the FIFOs. If IFCLKSRC = 0, the external clock ...
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These flags can be programmed to represent various FIFO flags using four select bits for each FIFO. The 4-bit coding for all four flags is the same, as shown in Table 9-2. . Table 9-2. FIFO Flag 4-bit Coding FLAGx3 ...
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Send the actual value to write to the register Register (in this case 0x1C) g. Command address write of address 0x3C h. Command data write of upper nibble of the register value (0x01) i. Command data write of lower ...
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EPxPKTLENH/L Registers 0x0A–0x11 The external master can use these registers to set smaller packet sizes than the physical buffer size (refer to the previously described EPxCFG registers). The default packet size is 512 bytes for all endpoints. Note that ...
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Following is the bit definition for the same register when the device is operating at full speed and the endpoint is not configured as isochronous endpoint. Full Speed Non-ISO Mode: EP2PFL, EP4PFL, EP6PFL, EP8PFL Bit # ...
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EPxxFLAGS Registers 0x1E–0x1F The EPxxFLAGS provide an alternate way of checking the status of the endpoint FIFO flags. If enabled, the SX2 can interrupt the external master when a flag is asserted, and the external master can read these ...
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INTENABLE Register 0x2E This register is used to enable/disable the various interrupt sources, and by default all interrupts are enabled. INTENABLE Bit # SETUP EP0 FLAGS 1 1 ENUM Bit Name BUF OK Read/Write ...
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Absolute Maximum Ratings Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Supplied...... 0°C to +70°C Supply Voltage to Ground Potential................–0.5V to +4.0V DC Input Voltage to Any Pin ........................................ 5.25V DC Voltage Applied to Outputs in High-Z ...
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Command Interface Figure 13-1. Command Synchronous Read Timing Diagram IFCLK SLRD INT# DATA SLOE Table 13-1. Command Synchronous Read Parameters with Internally Sourced IFCLK Parameter t IFCLK period IFCLK t SLRD to Clock Setup Time SRD t Clock to ...
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Figure 13-2. Command Synchronous Write Timing Diagram IFCLK SLWR DATA READY Table 13-3. Command Synchronous Write Parameters with Internally Sourced IFCLK Parameter t IFCLK Period IFCLK t SLWR to Clock Setup Time SWR t Clock to SLWR Hold Time WRH ...
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Table 13-5. Command Read Parameters Parameter t SLRD Pulse Width LOW RDpwl t SLRD Pulse Width HIGH RDpwh t INTERRUPT to SLRD IRD t SLRD to INTERRUPT XINT t SLOE Turn on to FIFO Data Valid OEon t SLOE Turn ...
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Table 13-7. Slave FIFO Synchronous Read with Internally Sourced IFCLK Parameter t IFCLK Period IFCLK t SLRD to Clock Setup Time SRD t Clock to SLRD Hold Time RDH t SLOE Turn on to FIFO Data Valid OEon t SLOE ...
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Table 13-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK Parameter t IFCLK Period IFCLK t SLWR to Clock Setup Time SWR t Clock to SLWR Hold Time WRH t FIFO Data to Clock Setup Time SFD t Clock ...
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Figure 13-8. Slave FIFO Synchronous Write Sequence and Timing Diagram t IFCLK IFCLK t SFA FIFOADR >= t SWR SLWR t t FDH SFD X-4 DATA PKTEND Figure 13-8. shows a scenario where two packets are being committed. The first ...
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Figure 13-10. Slave FIFO Asynchronous Read Timing Diagram SLRD FLAGS DATA SLOE Table 13-14. Slave FIFO Asynchronous Read Parameters Parameter t SLRD Pulse Width Low RDpwl t SLRD Pulse Width HIGH RDpwh t SLRD to FLAGS Output Propagation Delay XFLG ...
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Figure 13-12. Slave FIFO Asynchronous Packet End Strobe Timing Diagram PKTEND FLAGS Table 13-16. Slave FIFO Asynchronous Packet End Strobe Parameters Parameter t PKTEND Pulse Width LOW PEpwl t PKTEND Pulse Width HIGH PWpwh t PKTEND to FLAGS Output Propagation ...
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Slave FIFO Output Enable Following timings are applicable to synchronous and asynchronous interfaces. Figure 13-15. Slave FIFO Output Enable Timing Diagram SLOE DATA Table 13-19. Slave FIFO Output Enable Parameters Parameter t SLOE assert to FIFO DATA Output OEon ...
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Figure 13-16. shows the timing relationship of the SLAVE FIFO signals during a synchronous FIFO read using IFCLK as the synchronizing clock. The diagram illustrates a single read followed by a burst read the FIFO address ...
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Figure 13-18. shows the timing relationship of the SLAVE FIFO signals during a synchronous write using IFCLK as the synchro- nizing clock. The diagram illustrates a single write followed by burst write of 3 bytes and committing all 4 bytes ...
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Figure 13-20. Slave FIFO Asynchronous Read Sequence of Events Diagram SLOE SLRD FIFO POINTER N N FIFO DATA BUS Not Driven Driven: X Figure 13-20. diagrams the timing relationship of the SLAVE FIFO signals during an asynchronous FIFO read. It ...
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Default Descriptor //Device Descriptor 18, //Descriptor length 1, //Descriptor type 00,02, //Specification Version (BCD) 00, //Device class 00, //Device sub-class 00, //Device sub-sub-class 64, //Maximum packet size LSB(VID),MSB(VID),//Vendor ID LSB(PID),MSB(PID),//Product ID LSB(DID),MSB(DID),//Device ID 1, //Manufacturer string index 2, //Product ...
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Descriptor 7, //Descriptor length 5, //Descriptor type 0x86, //Endpoint number, and direction 2, //Endpoint type 0x00, //Maximum packet ...
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Descriptor 7, //Descriptor length 5, //Descriptor type 0x86, //Endpoint number, and direction 2, //Endpoint type 0x40, //Maximum packet size (LSB) 0x00, //Max packet size (MSB) 0x00, //Polling interval //Endpoint Descriptor 7, //Descriptor length 5, //Descriptor type 0x88, //Endpoint number, ...
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General PCB Layout Guidelines The following recommendations should be followed to ensure reliable high-performance operation. At least a four-layer impedance controlled boards are required ■ to maintain signal quality. Specify impedance targets (ask your board vendor what they ■ ...
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... Ordering Information Ordering Code CY7C68001-56PVC CY7C68001-56LFC CY7C68001-56PVXC CY7C68001-56LFXC CY3682 CY7C68001-56LTXC 18. Package Diagrams Figure 18-1. 56-Pin Shrunk Small Outline Package 056 Document #: 38-08013 Rev. *J Package Type 56 SSOP 56 QFN 56 SSOP, Pb-free 56 QFN, Pb-free EZ-USB SX2 Development Kit 56 QFN, Pb-free CY7C68001 51-85062-*C Page [+] Feedback ...
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Document #: 38-08013 Rev. *J Figure 18-2. 56-Pin QFN (8X8 mm) Figure 18-3. 56-Pin Sawn QFN (8X8X1.00 mm) CY7C68001 51-85144 *G 51-85187 *D Page [+] Feedback ...
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Document History Page Description Title: CY7C68001 EZ-USB SX2™ High Speed USB Interface Device Document Number: 38-08013 Submission Origin of REV. ECN No. Date Change ** 111807 06/07/02 BHA *A 123155 02/07/03 BHA *B 126324 07/02/03 MON *C 129463 10/07/03 ...
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Description Title: CY7C68001 EZ-USB SX2™ High Speed USB Interface Device Document Number: 38-08013 *D 130447 12/17/03 KKU *E 243316 See ECN KKU *F 329238 See ECN KEV *G 392570 See ECN KEV *H 411515 See ECN BHA *I 2665531 02/26/2009 ...
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... Document #: 38-08013 Rev. *J PSoC Designer™ trademark and PSoC® registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips ...