74AUP1G00 PHILIPS [NXP Semiconductors], 74AUP1G00 Datasheet
74AUP1G00
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74AUP1G00 Summary of contents
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... Low-power 2-input NAND gate Rev. 02 — 29 June 2006 1. General description The 74AUP1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V ...
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... GND 001aaf016 Fig 4. Pin configuration SOT353-1 (TSSOP5) 74AUP1G00_2 Product data sheet Description TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 XSON6 plastic extremely thin small outline package; no leads; ...
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... < Active mode Power-down mode +125 C amb derates linearly with 4.0 mW/K. tot derates linearly with 2.4 mW/K. tot Rev. 02 — 29 June 2006 74AUP1G00 Low-power 2-input NAND gate Output Min Max Unit 0.5 +4 [1] 0.5 +4.6 ...
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... 1 1 2 3 2 4 Rev. 02 — 29 June 2006 74AUP1G00 Low-power 2-input NAND gate Min Max 0.8 3 3.6 40 +125 0 200 Min Typ Max 2.0 - ...
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... 2 4 GND Rev. 02 — 29 June 2006 74AUP1G00 Low-power 2-input NAND gate Min Typ Max - - - - - - - - 0 1 ...
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... 3 0 GND GND. CC Rev. 02 — 29 June 2006 74AUP1G00 Low-power 2-input NAND gate Min Typ Max - - 0 0.30 ...
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... see Figure Rev. 02 — 29 June 2006 74AUP1G00 Low-power 2-input NAND gate [1] Min Typ Max Unit - 17 2.5 5.3 11.0 ns 2.0 3.8 6.8 ns 1.6 3.1 5.3 ns 1.3 2.5 4.0 ns 1.0 2.2 3 ...
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... see Figure Rev. 02 — 29 June 2006 74AUP1G00 Low-power 2-input NAND gate [1] Min Typ [ 2.6 - 2.8 - 2.9 - 3.1 - 3 +125 C Min Max Min 2.1 12.2 2 ...
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... input M GND t PHL output Table 10. Input 0 Rev. 02 — 29 June 2006 74AUP1G00 Low-power 2-input NAND gate + +125 C Min Max Min 3.1 16.5 3.1 2.5 10.5 2.5 2.0 8.3 2.0 1.5 6.4 1.5 1.4 5.7 1.4 4.1 22.6 4.1 2.9 14.0 2.9 2.3 11.1 2.3 2.1 8.5 2.1 2.1 7.6 2.1 ...
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... PULSE DUT GENERATOR for measuring propagation delays, setup and hold times and pulse width R L Rev. 02 — 29 June 2006 74AUP1G00 Low-power 2-input NAND gate V EXT 001aac521 of the pulse generator EXT ...
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... 1 scale (1) ( 0.30 0.25 2.25 1.35 0.65 0.15 0.08 1.85 1.15 REFERENCES JEDEC JEITA MO-203 SC-88A Rev. 02 — 29 June 2006 74AUP1G00 Low-power 2-input NAND gate detail 2.25 0.46 1.3 0.425 0.3 0.1 2.0 0.21 EUROPEAN PROJECTION © ...
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... scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA MO-252 Rev. 02 — 29 June 2006 74AUP1G00 Low-power 2-input NAND gate 4 ( EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2006. All rights reserved. SOT886 ISSUE DATE 04-07-15 04-07- ...
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... Product data sheet scale 1.05 0.35 0.40 0.55 0.35 0.95 0.27 0.32 REFERENCES JEDEC JEITA Rev. 02 — 29 June 2006 74AUP1G00 Low-power 2-input NAND gate SOT891 2 mm EUROPEAN ISSUE DATE PROJECTION 05-03-11 05-04-06 © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Revision history Table 13. Revision history Document ID Release date 74AUP1G00_2 20060629 • Modifications: ESD HBM and C • Added type number 74AUP1G00GF (XSON6/SOT891) package 74AUP1G00_1 20050711 74AUP1G00_2 Product data sheet Data sheet status Change notice Product data sheet - values modified in Section ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Rev. 02 — 29 June 2006 74AUP1G00 Low-power 2-input NAND gate © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. All rights reserved. Date of release: 29 June 2006 Document identifier: 74AUP1G00_2 ...