74lvc1g79 NXP Semiconductors, 74lvc1g79 Datasheet

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74lvc1g79

Manufacturer Part Number
74lvc1g79
Description
Single D-type Flip-flop; Positive-edge Trigger
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.
Information on the data input is transferred to the Q-output on the LOW-to-HIGH transition
of the clock pulse. The D-input must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
74LVC1G79
Single D-type flip-flop; positive-edge trigger
Rev. 07 — 29 August 2007
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
ESD protection:
Specified from 40 C to +125 C
24 mA output drive (V
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CC
= 3.0 V)
Product data sheet
OFF
. The I
OFF

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74lvc1g79 Summary of contents

Page 1

... Single D-type flip-flop; positive-edge trigger Rev. 07 — 29 August 2007 1. General description The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH transition of the clock pulse. The D-input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation ...

Page 2

... C to +125 C 74LVC1G79GV +125 C 74LVC1G79GM +125 C 74LVC1G79GF +125 C 4. Marking Table 2. Marking codes Type number 74LVC1G79GW 74LVC1G79GV 74LVC1G79GM 74LVC1G79GF 5. Functional diagram mna440 Fig 1. Logic symbol 74LVC1G79_7 Product data sheet Name Description TSSOP5 plastic thin shrink small outline package; ...

Page 3

... Transparent top view Fig 5. Pin configuration SOT886 SOT886/SOT891 Rev. 07 — 29 August 2007 74LVC1G79 mna442 74LVC1G79 GND 3 4 001aaf410 Transparent top view Fig 6. Pin configuration SOT891 Description data input data pulse input ...

Page 4

... > < Active mode Power-down mode +125 C amb derates linearly with 4.0 mW/K. tot derates linearly with 2.4 mW/K. tot Rev. 07 — 29 August 2007 74LVC1G79 Output Min Max Unit 0.5 +6 [1] 0.5 +6 [1][2] 0 ...

Page 5

... GND 5 5 Rev. 07 — 29 August 2007 74LVC1G79 Min Typ Max Unit 1. +125 - - 20 ns ns/V [1] ...

Page 6

... GND 1. 5 per pin 3.3 V and amb Rev. 07 — 29 August 2007 74LVC1G79 Single D-type flip-flop; positive-edge trigger [1] Min Typ Max - 0 500 - ...

Page 7

... 5.5 V 200 CC [3] = GND 3 and V = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. amb where Rev. 07 — 29 August 2007 74LVC1G79 Single D-type flip-flop; positive-edge trigger Figure + +125 C Unit [1] Typ Max Min 1.0 3.6 9.9 1.0 0.5 2.3 7.0 0.5 0.5 2.6 6.0 0.5 0.5 2 ...

Page 8

... GND 1/f max GND PHL Table 9. Rev. 07 — 29 August 2007 74LVC1G79 Single D-type flip-flop; positive-edge trigger PLH V M mna443 PLH mna647 © NXP B.V. 2007. All rights reserved ...

Page 9

... DUT the pulse generator. o Load Rev. 07 — 29 August 2007 74LVC1G79 Output 1.5 V 1 EXT mna616 V EXT PLH 1 k open ...

Page 10

... 1 scale (1) ( 0.30 0.25 2.25 1.35 0.65 0.15 0.08 1.85 1.15 REFERENCES JEDEC JEITA MO-203 SC-88A Rev. 07 — 29 August 2007 74LVC1G79 Single D-type flip-flop; positive-edge trigger detail 2.25 0.46 1.3 0.425 0.3 0.1 2.0 0.21 ...

Page 11

... scale 3.1 1.7 3.0 0.6 0.95 2.7 1.3 2.5 0.2 REFERENCES JEDEC JEITA SC-74A Rev. 07 — 29 August 2007 74LVC1G79 Single D-type flip-flop; positive-edge trigger detail 0.33 0.2 0.2 0.1 0.23 EUROPEAN PROJECTION SOT753 ISSUE DATE 02-04-16 06-03-16 © ...

Page 12

... scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA MO-252 Rev. 07 — 29 August 2007 74LVC1G79 Single D-type flip-flop; positive-edge trigger 4 ( EUROPEAN PROJECTION SOT886 ISSUE DATE 04-07-15 04-07-22 © NXP B.V. 2007. All rights reserved ...

Page 13

... scale 1.05 0.35 0.40 0.55 0.35 0.95 0.27 0.32 REFERENCES JEDEC JEITA Rev. 07 — 29 August 2007 74LVC1G79 Single D-type flip-flop; positive-edge trigger 4 ( EUROPEAN PROJECTION © NXP B.V. 2007. All rights reserved. SOT891 ISSUE DATE 05-04-06 07-05- ...

Page 14

... Product specification Product specification Product specification Product specification Product specification Rev. 07 — 29 August 2007 74LVC1G79 Single D-type flip-flop; positive-edge trigger Change notice Supersedes - 74LVC1G79_6 updated. - 74LVC1G79_5 - 74LVC1G79_4 - 74LVC1G79_3 - 74LVC1G79_2 - 74LVC1G79_1 - - © NXP B.V. 2007. All rights reserved ...

Page 15

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 07 — 29 August 2007 74LVC1G79 Single D-type flip-flop; positive-edge trigger © NXP B.V. 2007. All rights reserved ...

Page 16

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 29 August 2007 Document identifier: 74LVC1G79_7 ...

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