AD5065 Analog Devices, AD5065 Datasheet
AD5065
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AD5065 Summary of contents
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... LSB. The parts use a versatile 3-wire, low power Schmitt trigger serial interface that operates at clock rates MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The reference for the AD5025/ AD5045/AD5065 are supplied from an external pin and a refer- SCLK SYNC INTERFACE ...
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... Power Supply Bypassing and Grounding ................................ 22 Microprocessor Interfacing ....................................................... 23 Applications Information .............................................................. 24 Using a Reference as a Power Supply for the AD5025/AD5045/AD5065 ....................................................... 24 Bipolar Operation Using the AD5025/AD5045/AD5065 ..... 24 Using the AD5025/AD5045/AD5065 with a Galvanically Isolated Interface ................................................. 24 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25 ...
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... A ±1 LSB ±2 2 5.5 V REF DD ±1.8 mV Code 512 (AD5065), Code 128 (AD5045), Code 32 (AD5025) loaded to DAC register μV/°C ±0.07 % FSR All 1s loaded to DAC register, V ±0.05 % FSR ppm Of FSR/°C 40 μV Due to single channel full-scale output change kΩ ...
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... Temperature range is −40°C to +125°C, typical at 25° grade offered in AD5065 only. 3 Linearity calculated using a reduced code range—AD5065: Code 512 to Code 65,024; AD5045: Code 128 to Code 16,256; AD5025: Code 32 to Code 4064. Output unloaded. 4 Guaranteed by design and characterization; not production tested. ...
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... OUTPUT OH PIN C L 50pF 2mA I OH Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications Rev Page AD5025/AD5045/AD5065 + V )/2. See Figure 3 and IL IH Min Typ Max 16 ...
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... AD5025/AD5045/AD5065 SCLK YNC DIN DB31 1 LDAC 2 LDAC CLR V OUT PDL 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. SCLK SYNC DB31 DIN INPUT WORD FOR DAC N SDO 1 LDAC CLR PDL DAISY-CHAIN MODE, LDAC MUST BE USED ASYNCHRONOUSLY. ...
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... 0.3 V maximum rating conditions for extended periods may affect DD −0 0.3 V device reliability. DD −40°C to +125°C −65°C to +150°C ESD CAUTION 150°C (T − T )/θ J MAX A JA 150.4°C/W 240°C 260°C Rev Page AD5025/AD5045/AD5065 ...
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... Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data can be transferred at rates MHz. LDAC SCLK 1 14 SYNC DIN 2 13 AD5025 PDL DD AD5045/ AD5065 V A GND 4 11 REF TOP VIEW OUT OUT (Not to Scale) ...
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... TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 512 16,640 32,768 DAC CODE Figure 6. AD5065 INL 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1024 1536 2048 2560 DAC CODE Figure 7. AD5045 INL 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1024 1536 2048 2560 DAC CODE Figure 8 ...
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... AD5025/AD5045/AD5065 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 512 16,640 32,768 DAC CODE Figure 12. Total Unadjusted Error (TUE) vs. DAC Code 1 25°C A 1.4 1.2 1.0 0.8 0.6 MAX INL ERROR @ V 0.4 0.2 0 –0.2 –0.4 MIN INL ERROR @ V –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 2.0 2.5 3.0 3.5 4.0 REFERENCE VOLTAGE (V) Figure 13. INL vs. Reference Input Voltage 1 ...
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... Figure 21. Settling Time and Typical Output Slew Rate 1 3 5.50 CH1 CH1 2V 1.4 1.5 Rev Page AD5025/AD5045/AD5065 4.096V DD REF T = 25ºC A 1/4 SCALE TO 3/4 SCALE 3/4 SCALE TO 1/4 SCALE OUTPUT LOADED WITH 5kΩ AND 200pF TO GND TIME (µs) POR V OUT CH3 2V ...
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... AD5025/AD5045/AD5065 CH1 = SCLK 1 CH2 = OUT DD POWER-UP TO MIDSCALE 2 CH1 5V CH2 500mV M2µs T 55% Figure 24. Exiting Power-Down to Midscale –1 –2 –3 0 2.5 5.0 TIME (μs) Figure 25. Digital-to-Analog Glitch Impulse 5V 4.096V DD REF 25º –1 –2 – ...
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... OUT –0.02 –0.04 –0.06 –0.08 –0.10 2.5V –25 10000 CH1 Figure 35. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale, Rev Page AD5025/AD5045/AD5065 CODE = MIDSCALE 4.096V DD REF V = 5.5V DD –20 –15 –10 – CURRENT (mA) Figure 33. Typical Output Load Regulation ...
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... AD5025/AD5045/AD5065 V OUT SCLK CH1 50mV CH2 5V M4µs T 8.6% Figure 36. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale, 5 kΩ/200 pF Load V OUT SCLK CH1 20mV CH2 5V M4µs T 8.6% Figure 37. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, No Load ...
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... OUT OUT region of the transfer function. Offset error is measured on the part with Code 512 (AD5065), Code 128 (AD5045), and Code 32 (AD5025) loaded into the DAC register. It can be negative or positive and is expressed in millivolts. Offset Error Drift Offset error drift is a measure of the change in offset error with a change in temperature ...
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... AD5025/AD5045/AD5065 Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC measured by loading one of the input registers with a full-scale code change (all 0s to all 1s or vice versa) while keeping LDAC high, and then pulsing LDAC low and monitoring the output of the DAC whose digital code has not changed ...
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... DIGITAL-TO-ANALOG CONVERTER The AD5025/AD5045/AD5065 are single 12-/14-/16-bit, serial input, voltage output DACs. The parts operate from supply voltages of 4 5.5 V. Data is written to the AD5025/AD5045/AD5065 in a 32-bit word format via a 3-wire serial interface. The AD5025/ AD5045/AD5065 incorporate a power-on reset circuit that ensures the DAC output powers known output state ...
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... ADDRESS BITS DB31 (MSB COMMAND BITS ADDRESS BITS D15 D14 D13 D12 D11 D10 D9 Figure 41. AD5065 Input Register Content D13 D12 D11 D10 DATA BITS Figure 42. AD5045 Input Register Content D11 D10 ...
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... The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 32-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the AD5025/AD5045/AD5065 compatible nd with high speed DSPs. On the 32 ...
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... Note that this is outside the linear region of the DAC; by connecting the POR pin high, the AD5025/AD5045/AD5065 output powers up to midscale. The output remains powered up at this level until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while the process of powering up ...
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... CLEAR CODE REGISTER The AD5025/AD5045/AD5065 have a hardware CLR pin that is an asynchronous clear input. The CLR input is falling edge sensi- tive. Bringing the CLR line low clears the contents of the input register and the DAC registers to the data contained in the user- configurable CLR register, and sets the analog outputs accordingly (see Table 13) ...
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... The printed circuit board (PCB) containing the AD5025/AD5045/ AD5065 should have separate analog and digital sections. If the AD5025/AD5045/AD5065 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only ...
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... Data is transmitted MSB first. To load data to the AD5025/AD5045/ AD5065, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. ...
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... USING A REFERENCE AS A POWER SUPPLY FOR THE AD5025/AD5045/AD5065 Because the supply current required by the AD5025/AD5045/ AD5065 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the parts (see Figure 50). This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than for example ...
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... Figure 53. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Package Description 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP Rev Page AD5025/AD5045/AD5065 0.75 0.60 0.45 Package Option Accuracy Resolution RU-14 ±0.25 LSB INL 12 bits RU-14 ±0.25 LSB INL ...
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... AD5025/AD5045/AD5065 NOTES Rev Page ...
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... NOTES AD5025/AD5045/AD5065 Rev Page ...
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... AD5025/AD5045/AD5065 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06844-0-10/08(0) Rev Page ...