AD673 Analog Devices, AD673 Datasheet
AD673
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AD673 Summary of contents
Page 1
... SiCr thin-film resistor ladder network insures high accuracy, which is maintained with a temperature compensated sub-surface Zener reference. Operating on supplies and – –15 V, the AD673 will accept analog inputs + – The trailing edge of a positive pulse on the CONVERT line initiates the 20 s conversion cycle ...
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... Positive True Binary Positive True Offset Binary ) 3.2 ) 0.5 2.0 0 +4.5 +5.0 +7.0 –11.4 –15 –16 potentiometer in place of the 15 –2– AD673S Min Typ Max 8 1/2 1/2 1/2 1/2 2 1/2 1/2 1/2 1 –55 +125 3.0 5.0 7.0 0 +10 –5 +5 Positive True Binary Positive True Offset Binary 3 ...
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... For details on grade and package offering screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook . FUNCTIONAL DESCRIPTION A block diagram of the AD673 is shown in Figure 1. The posi- tive CONVERT pulse must be at least 500 ns wide. DR goes high within 1.5 s after the leading edge of the convert pulse in- dicating that the internal logic has been reset ...
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... Figure 5 shows the nominal transfer curve near zero for an AD673 in unipolar mode. The code transitions are at the edges of the nominal bit weights. In some applications it will be prefer- able to offset the code transitions so that they fall between the nominal bit weights, as shown in the offset characteristics ...
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... A SHA can also be used to accurately define the exact point in time at which the signal is sampled. For the AD673, a SHA can also serve as a high input impedance buffer. Figure 8 shows the AD673 connected to the AD582 monolithic SHA for high speed signal acquisition ...
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... It is recommended that a parallel pair of back-to-back protection diodes be connected between the commons if they are not connected locally. CONTROL AND TIMING OF THE AD673 The operation of the AD673 is controlled by two inputs: CON- VERT and DATA ENABLE. Starting a Conversion The conversion cycle is initiated by a positive-going CONVERT pulse at least 500 ns wide ...
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... Figure 12. Typical AD673 Timing Diagram REV. A CONVERT Pulse Generation The AD673 is tested with a CONVERT pulse width of 500 ns and will typically operate with a pulse as short as 300 ns. How- ever, some microprocessors produce active WR pulses which are shorter than this. Either of the circuits shown in Figure 13 can be used to generate an adequate CONVERT pulse for the AD673 ...
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... AD673 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Pin Ceramic DIP (D-20) 20-Pin Plastic DIP (N-20) –8– REV. A ...