AD9243 Analog Devices, AD9243 Datasheet

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AD9243

Manufacturer Part Number
AD9243
Description
Complete 14-Bit, 3 MSPS Monolithic A/D Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9243

Resolution (bits)
14bit
# Chan
1
Sample Rate
3MSPS
Interface
Par
Analog Input Type
Diff-Uni,SE-Uni
Ain Range
(2Vref) p-p,2 V p-p,5V p-p,Uni (Vref) x 2,Uni 2.0V,Uni 5.0V
Adc Architecture
Pipelined
Pkg Type
QFP

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a
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PRODUCT DESCRIPTION
The AD9243 is a 3 MSPS, single supply, 14-bit analog-to-
digital converter (ADC). It combines a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid implementations at a fraction of the
power consumption and cost. It is a complete, monolithic ADC
with an on-chip, high performance, low noise sample-and-hold
amplifier and programmable voltage reference. An external refer-
ence can also be chosen to suit the dc accuracy and temperature
drift requirements of the application. The device uses a multistage
differential pipelined architecture with digital output error correc-
tion logic to guarantee no missing codes over the full operating
temperature range.
The input of the AD9243 is highly flexible, allowing for easy
interfacing to imaging, communications, medical, and data-
acquisition systems. A truly differential input structure allows
for both single-ended and differential input interfaces of varying
input spans. The sample-and-hold amplifier (SHA) is equally
suited for both multiplexed systems that switch full-scale voltage
levels in successive channels as well as sampling single-channel
inputs at frequencies up to and beyond the Nyquist rate. Also,
the AD9243 performs well in communication systems employ-
ing Direct-IF Down Conversion since the SHA in the differen-
tial input mode can achieve excellent dynamic performance well
beyond its specified Nyquist frequency of 1.5 MHz.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an
overflow condition which can be used with the most significant
bit to determine low or high overflow.
FEATURES
Monolithic 14-Bit, 3 MSPS A/D Converter
Low Power Dissipation: 110 mW
Single +5 V Supply
Integral Nonlinearity Error: 2.5 LSB
Differential Nonlinearity Error: 0.6 LSB
Input Referred Noise: 0.36 LSB
Complete: On-Chip Sample-and-Hold Amplifier and
Signal-to-Noise and Distortion Ratio: 79.0 dB
Spurious-Free Dynamic Range: 91.0 dB
Out-of-Range Indicator
Straight Binary Output Data
44-Lead MQFP
Voltage Reference
PRODUCT HIGHLIGHTS
The AD9243 offers a complete single-chip sampling 14-bit,
analog-to-digital conversion function in a 44-lead Metric Quad
Flatpack.
Low Power and Single Supply
The AD9243 consumes only 110 mW on a single +5 V power
supply.
Excellent DC Performance Over Temperature
The AD9243 provides no missing codes, and excellent tempera-
ture drift performance over the full operating temperature range.
Excellent AC Performance and Low Noise
The AD9243 provides nearly 13 ENOB performance and has an
input referred noise of 0.36 LSB rms.
Flexible Analog Input Range
The versatile onboard sample-and-hold (SHA) can be configured
for either single ended or differential inputs of varying input spans.
Flexible Digital Outputs
The digital outputs can be configured to interface with +3 V and
+5 V CMOS logic families.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
SENSE
CAPB
CAPT
VREF
VINA
VINB
CML
SHA
SELECT
Complete 14-Bit, 3.0 MSPS
MODE
Monolithic A/D Converter
FUNCTIONAL BLOCK DIAGRAM
A/D
GAIN = 16
MDAC1
REFCOM
5
5
World Wide Web Site: http://www.analog.com
CLK
1V
DIGITAL CORRECTION LOGIC
AD9243
OUTPUT BUFFERS
A/D
GAIN = 8
MDAC2
4
AVDD
AVSS
4
14
© Analog Devices, Inc., 1998
DVDD
DVSS
A/D
AD9243
GAIN = 8
MDAC3
4
4
DRVDD
DRVSS
A/D
4
OTR
BIT 1
(MSB)
BIT 14
(LSB)

Related parts for AD9243

AD9243 Summary of contents

Page 1

... The AD9243 offers a complete single-chip sampling 14-bit, analog-to-digital conversion function in a 44-lead Metric Quad Flatpack. Low Power and Single Supply The AD9243 consumes only 110 single +5 V power supply. Excellent DC Performance Over Temperature The AD9243 provides no missing codes, and excellent tempera- ture drift performance over the full operating temperature range ...

Page 2

... DRVDD Supply Current IAVDD IDRVDD IDVDD POWER CONSUMPTION NOTES REF 2 Including internal reference. 3 Excluding internal reference. 4 Load regulation with 1 mA load current (in addition to that required by the AD9243). Specification subject to change without notice MSPS, VREF = 2.5 V, VINB = 2 SAMPLE AD9243 14 3 0.9 0.36 2.5 0.6 1.0 2.5 0.7 14 0.3 1 ...

Page 3

... AD9243 +3.5 +1 +4.5 +2.4 +0.4 +0.1 5 +2.4 +0.7 AD9243 Units dB min dB typ dB typ Bits min Bits typ Bits typ dB min dB typ dB typ dB max dB typ dB typ dB typ dB typ MHz typ MHz typ ns typ ps rms typ ns typ ns typ Units V min V max A max ...

Page 4

... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9243 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

Page 5

... The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered dBFS (always related back to converter full scale). –5– AD9243 ...

Page 6

... AD9243 Typical Differential AC Characterization Curves/Plots 90 14.7 85 13.8 80 13.0 –0.5dBFS 75 12.2 –6.0dBFS 70 11.3 65 10.5 –20.0dBFS 60 9.7 55 8.8 50 8.0 100k 1M 10M 20M INPUT FREQUENCY – Hz Figure 2. SINAD vs. Input Frequency (Input Span = 2 14.7 85 13.8 13.0 80 –0.5dBFS 75 12.2 –6.0dBFS 70 11.3 65 10.5 60 9.7 –20.0dBFS 55 8.8 50 8.0 100k 1M 10M 20M INPUT FREQUENCY – ...

Page 7

... INPUT FREQUENCY – Hz Figure 18. THD vs. Input Frequency (Input Span = 2 –7– AD9243 = 3.00 MSPS +25 C, SAMPLE A 4,343,995 439,383 356,972 N–1 N N+1 CODE Figure 13. “Grounded-Input” Histogram (Input Span = ...

Page 8

... VREF is the voltage at the VREF pin. While an infinite combination of VINA and VINB inputs exist that satisfy Equation 2, there is an additional limitation placed on the inputs by the power supply voltages of the AD9243. The power supplies bound the valid operating range for VINA and VINB. The condition, AVSS – ...

Page 9

... V input span) and matched input impedance for VINA and VINB. Note that only a slight degradation in dc linearity performance exists between the 2 V and 5 V input span as specified in the AD9243 “DC SPECIFICATIONS.” ...

Page 10

... VINA and/or VINB) and analog ground. Since this additional shunt capacitance combines with the equivalent input capaci- tance of the AD9243, a lower series resistance can be selected to establish the filter’s cutoff frequency while not degrading the distortion performance of the device. The shunt capacitance ...

Page 11

... VREF pin to be driven by an external voltage reference. The actual reference voltages used by the internal circuitry of the AD9243 appear on the CAPT and CAPB pins. For proper operation when using the internal or an external reference necessary to add a capacitor network to decouple these pins. ...

Page 12

... Furthermore, it allows the AD9243 to be configured for span using op amps specified for + operation. Single-ended operation requires that VINA coupled to the input signal source while VINB of the AD9243 be biased to the appropriate voltage corresponding to a midscale code transition. Note that signal inversion may be easily accom- plished by transposing VINA and VINB ...

Page 13

... AD9243 differentially. Since the signal swing requirements of each input is reduced by a factor of two in the differential mode, the AD9243 can be configured for input span system. This allows various high performance op amps specified for +5 V and 5 V operation to be configured in various differential driver topologies ...

Page 14

... AD9243 If the application requires the largest single-ended input range (i.e the AD9243, the op amp will require larger supplies to drive it. Various high speed amplifiers in the “Op Amp Selection Guide” of this data sheet can be selected to accommodate a wide range of supply options. Once again, clamping the output of the amplifier should be considered for these applications ...

Page 15

... Figure 27. USING THE INTERNAL REFERENCE Single-Ended Input with Figure 36 shows how to connect the AD9243 for input range via pin strapping the SENSE pin. An intermediate input range VREF can be established using the resistor programmable configuration in Figure 38 and connecting VREF to VINB ...

Page 16

... set at midsupply by connecting the transformers center CM tap to CML of the AD9243. VREF can be configured for 2 connecting SENSE to either VREF or REFCOM respectively. Note that the valid input range for each of the differential inputs is one half of the single-ended input and thus becomes V – ...

Page 17

... CAPB Decoupling Network, and driving these pins directly. Variable Input Span with Figure 39 shows an example of the AD9243 configured for an input span of 2 VREF centered at 2 external 2.5 V reference drives the VINB pin thus setting the common-mode voltage at 2.5 V. The input span can be independently set by a voltage divider consisting of R1 and R2 which generates the VREF signal ...

Page 18

... UNDER = “1” it should be retimed by the original clock at the last step. Most of the power dissipated by the AD9243 is from the analog power supply. However, lower clock speeds will reduce digital current slightly. Figure 44 shows the relationship between power and clock rate ...

Page 19

... The AVSS, DVSS and DRVSS pins must be joined together directly under the AD9243. A solid ground plane under the A/D is acceptable if the power and ground return currents are managed carefully. Alternatively, the ground plane under the A/D may ...

Page 20

... Nyquist zone, the resultant frequency after sampling is 700 kHz. Figure 49 shows the typical performance of the AD9243 operating under these conditions. Figure 50 demon- strates how the AD9243 is still able to maintain a high degree of linearity and SFDR over a wide amplitude. –15 –30 – ...

Page 21

... AVSS1 AVSS2 AVDD1 AVDD2 REV. A DVDD DRVDD DVSS DRVSS Figure 51. Evaluation Board Schematic –21– AD9243 SJ5 SJ4 SJ3 SJ2 SJ1 JG1 ...

Page 22

... AD9243 Figure 52. Evaluation Board Component Side Layout (Not to Scale) Figure 53. Evaluation Board Solder Side Layout (Not to Scale) –22– REV. A ...

Page 23

... Figure 54. Evaluation Board Ground Plane Layout (Not to Scale) Figure 55. Evaluation Board Power Plane Layout (Not to Scale) REV. A –23– AD9243 ...

Page 24

... AD9243 1.03 (0.041) 0.73 (0.029) 0.25 (0.01) 0.23 (0.009) 0.13 (0.005) OUTLINE DIMENSIONS Dimensions shown in mm and (inches). 44-Lead Metric Quad Flatpack (MQFP) (S-44) 13.45 (0.530) 12.95 (0.510) 2.45 (0.096) 10.1 (0.398) MAX 9.90 (0.390 MIN 1 SEATING PIN 1 PLANE IDENTIFIER TOP VIEW (PINS DOWN) 11 MIN 12 0.45 (0.018) 0.8 (0.031) BSC 2.1 (0.083) 0.3 (0.012) 1.95 (0.077) –24– ...

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