AD9273 Analog Devices, AD9273 Datasheet
AD9273
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AD9273 Summary of contents
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... Medical imaging/ultrasound Automotive radar GENERAL DESCRIPTION The AD9273 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a low noise preamplifier (LNA) with a variable gain amplifier (VGA); an antialiasing filter (AAF); and a 12-bit, 10 MSPS to 50 MSPS analog-to- digital converter (ADC) ...
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... AD9273 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Product Highlights ........................................................................... 3 Specifications ..................................................................................... 4 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 8 Switching Specifications .............................................................. 9 ADC Timing Diagrams ................................................................. 10 Absolute Maximum Ratings .......................................................... 11 Thermal Impedance ................................................................... 11 ESD Caution ................................................................................ 11 Pin Configuration and Function Descriptions ........................... 12 Typical Performance Characteristics ........................................... 15 Equivalent Circuits ......................................................................... 19 REVISION HISTORY 7/09— ...
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... Fabricated in an advanced CMOS process, the AD9273 is available × 16 mm, RoHS compliant, 100-lead TQFP or a 144-ball BGA specified over the industrial temperature range of − ...
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... Rev Page Ω, LNA gain = 21.3 dB, LNA bias =mid- S AD9273-50 Max Min Typ Max Unit 15.6/17.9/21.3 dB 9.6/11.9/15.3 dB 733/550/367 mV p Ω 100 Ω 15 kΩ MHz 1.6/1.42/1.26 nV/√ ...
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... Rev Page AD9273 AD9273-50 Max Min Typ Max Unit ±10 % ±2 ns 1.94/1.64/1.38 nV/√Hz 10.3/8.6/6.7 dB 7.1/5.9/4.8 dB −30 dB +35 −35 +35 LSB 63.5 dBFS 56.5 dBFS −52 dBc − ...
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... Rev Page AD9273-50 Max Min Typ Max Unit 1.5 dB +1.6 −1.7 +1.7 dB −2.5 dB +1.6 −1.7 +1.7 dB 0.1 dB 1 dB/V 750 ns 10 MΩ 70 kΩ 5.4/7.3/10.9 mA/V 3.6 1.5 3.6 V 2.6/2.1/1.6 nV/√Hz 160/159/158 dBFS/√Hz −70 dBc 2 ...
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... Typ Max Min Typ 150 150 819 940 873 275 275 5 148 1.6 1 ± Rev Page AD9273 AD9273-50 Max Min Typ Max Unit 150 996 943 1072 mW 275 158 170 mW 1.6 mV/V 12 Bits ± ...
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... AD9273 DIGITAL SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f Table 2. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance 2 Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, STBY, SCLK) Logic 1 Voltage Logic 0 Voltage Input Resistance ...
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... FCO Full (t /24) − 300 (t SAMPLE SAMPLE Full (t /24) − 300 (t SAMPLE SAMPLE Full ±100 25°C <2 25°C 1 Full 8 25°C <1 Rev Page AD9273 Max Unit 50 MSPS ns ns /2) + 2.3 (t /2) + 3.1 ns SAMPLE ps ps /2) + 2.3 (t /2) + 3.1 ns SAMPLE /24) ns SAMPLE /24) (t /24) + 300 ps SAMPLE ...
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... AD9273 ADC TIMING DIAGRAMS N – 1 AIN t EH CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO DOUTx– DOUTx+ N – 1 AIN t EH CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO DOUTx– DOUTx ...
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... PCB with a solid ground plane (simulated). The exposed JA −0 +2.0 V pad is soldered to the PCB. −0 +3.9 V ESD CAUTION −0 +3.9 V −0 +2.0 V −40°C to +85°C −65°C to +150°C 150°C 300°C Rev Page AD9273 θ 1 θ θ Unit 20.3 N/A N/A °C/W 14 ...
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... LO-H 17 LOSW-H 18 LI-H 19 LG-H 20 AVDD2 21 AVDD1 22 CLK– 23 CLK+ 24 AVDD1 25 NOTES 1. THE EXPOSED PAD SHOULD BE TIED TO A QUIET ANALOG GROUND. EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9273 TOP VIEW (Not to Scale) Figure 4. TQFP Pin Configuration ...
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... Digital Clock Output True Frame Clock Digital Output Complement Frame Clock Digital Output True ADC D Digital Output Complement ADC D Digital Output True ADC C Digital Output Complement ADC C Digital Output True ADC B Digital Output Complement ADC B Digital Output True Rev Page AD9273 ...
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... AD9273 Pin No. TQFP BGA Name 45 M11 DOUTA− 46 L11 DOUTA+ 48 K11 STBY 49 J11 PDWN 51 K12 SCLK 52 J12 SDIO 53 H12 CSB LOSW LO-A 62 B10 LG-B 63 A10 LI-B 64 D10 LOSW-B 65 C10 LO-B 68 B11 LG-C 69 A11 LI-C 70 D11 LOSW-C 71 C11 LO-C 74 B12 LG-D 75 A12 LI-D 76 D12 LOSW-D 77 C12 LO-D 78 K10 CWD0− ...
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... GAIN ERROR (dB) Figure 9. Gain Error Histogram, GAIN –1.25 –1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25 CHANNEL-TO-CHANNEL GAIN MATCHING (dB) Figure 10. Gain Match Histogram, GAIN –1.25 –1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25 CHANNEL-TO-CHANNEL GAIN MATCHING (dB) Figure 11. Gain Match Histogram, GAIN+ = 1.3 V AD9273 /3, ...
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... AD9273 500k 450k 400k 350k 300k 250k 200k 150k 100k 50k 0 –7 –6 –5 –4 –3 –2 – CODES Figure 12. Output-Referred Noise Histogram, GAIN+ = 0.0 V 200k 180k 160k 140k 120k 100k 80k 60k 40k 20k 0 –7 –6 –5 –4 –3 –2 –1 ...
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... ADC OUTPUT LEVEL (dBFS) GAIN+ = 0.8V GAIN GAIN+ = 1.6V –35 –30 –25 –20 –15 –10 –5 ADC OUTPUT LEVEL (dBFS 0.01MHz IN1 IN2 –1dBFS –21dBFS IN IN 5MHz 2.3MHz 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 GAIN+ (V) Figure 23. IMD3 vs. GAIN+ AD9273 0 0 8MHz 1.5 1.6 ...
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... AD9273 5.00MHz, = 5.01MHz IN1 IN2 FUND2 LEVEL = FUND1 LEVEL – 20dB –20 –40 –60 GAIN –80 –100 –120 –40 –35 –30 –25 –20 –15 FUND1 LEVEL (dBFS) Figure 24. IMD3 vs. Fundamental 1 Amplitude (FUND1) Level GAIN+ = 0.8V GAIN+ = 1.6V –10 –5 0 Rev Page ...
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... Rev Page AVDDx 350Ω SDIO 30kΩ Figure 28. Equivalent SDIO Input Circuit DRVDD V V DOUTx– DOUTx DRGND Figure 29. Equivalent Digital Output Circuit 1kΩ SCLK, PDWN, OR STBY 30kΩ Figure 30. Equivalent SCLK, PDWN, or STBY Input Circuit AD9273 ...
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... AD9273 100Ω RBIAS Figure 31. Equivalent RBIAS Circuit AVDDx 70kΩ 1kΩ CSB Figure 32. Equivalent CSB Input Circuit VREF 6kΩ Figure 33. Equivalent VREF Circuit AVDDx Rev Page AVDD2 50Ω GAIN+ Figure 34. Equivalent GAIN+ Input Circuit 0.8V AVDD2 70kΩ 50Ω GAIN– ...
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... THEORY OF OPERATION ULTRASOUND The primary application for the AD9273 is medical ultrasound. Figure 37 shows a simplified block diagram of an ultrasound system. A critical function of an ultrasound system is the time gain control (TGC) compensation for physiological signal attenuation. Because the attenuation of ultrasound signals is exponential with respect to distance (time), a linear-in-dB VGA is the optimal solution ...
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... V – O LOSW-x channel to channel and part to part, depending on the LO-x application and layout of the PCB (see Figure 38 LG Rev Page CWD[7:0]+ CWD[7:0]– DOUTx+ SERIAL PIPELINE FILTER LVDS ADC DOUTx– AD9273 ...
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... C in terms because the dc levels at Pin LO-x FB Minimum R (Ω) R (Ω) C (pF 200 90 50 250 70 50 350 50 100 400 30 100 500 20 100 700 10 200 800 N/A 200 1000 N/A 200 1400 N/A AD9273 100M FB should (MHz ...
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... AD9273 LNA Noise The short-circuit noise voltage (input-referred noise impor- tant limit on system performance. The short-circuit input-referred noise voltage for the LNA is 1.4 nV/√ gain of 21.3 dB, including the VGA noise at a VGA postamp gain of 27 dB. These measurements, which were taken without a feedback resistor, provide the basis for calculating the input noise and noise figure (NF) performance of the configurations shown in Figure 41 ...
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... Register 0x2C (see Table 17) to connect to the noninverting AD9273 output to provide a differential output of the LNA. The LNA output 10nF full-scale voltage of the AD9273 is 4.4 V p-p, and the input full- LNA scale voltage is 2 attenuation is provided between 10nF the LNA output and the demodulator, the LNA input full-scale voltage must be limited ...
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... CHANNEL g LNA m LNA g m Figure 45. Typical Connection Interface with the AD8333 or AD8339 using the CWDx± Outputs AD9273 LNA LNA LNA Figure 46. Typical Connection Interface with the AD8333 or AD8339 using the LO-x and LOSW-x Outputs 600µH 2.5V 700Ω 600µH 600µ ...
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... The maximum number of channels combined must be considered when setting the load impedance for current-to-voltage conversion to ensure that the full-scale swing and common-mode voltage are within the operating limits of the AD9273. When interfacing to the AD8339, a common-mode voltage of 2.5 V and a full-scale swing of 2.8 V p-p are desired. This can be accomplished by connecting an inductor between each CWD output and a 2 ...
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... AD9273 Table 9. Sensitivity and Dynamic Range of Trade-Offs LNA Gain Input-Referred Full-Scale Input Noise Voltage (V/V) (dB) (V p-p) (nV/√Hz) 6 15.6 0.733 1.6 8 17.9 0.550 1.42 12 21.3 0.367 1.26 1 LNA: output full scale = 4.4 V p-p differential. 2 Filter: loss ~ 1 dB, NBW = 13.3 MHz, GAIN− ADC: 40 MSPS SNR p-p full-scale input. 4 Output dynamic range at minimum VGA gain (VGA dominated). ...
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... Figure 53. In either method, the GAIN+ and GAIN− pins should be dc-coupled and driven to accommodate a 1.6 V full-scale input. AD9273 – POSTAMP Rev Page 100Ω GAIN+ 0.01µF 50Ω GAIN– KELVIN 0.01µF CONNECTION Figure 52. Single-Ended GAIN± Pins Configuration AD9273 GAIN 0V TO 1.6V DC ...
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... AD9273 499Ω AD9273 ±0.4VDC AT 100Ω 0.8V CM GAIN+ 0.01µF AD8138 100Ω GAIN– ±0.4VDC AT 0.01µF 0.8V CM 499Ω Figure 53. Differential GAIN± Pins Configuration VGA Noise In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. The ...
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... AD9273 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9273, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. ...
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... ANALOG INPUT FREQUENCY (MHz) Figure 60. Ideal SNR vs. Analog Input Frequency and Jitter Power Dissipation and Power-Down Mode As shown in Figure 62, the power dissipated by the AD9273 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers ...
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... The AD9273 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. By asserting the STBY pin high, the AD9273 is placed into a standby mode. In this state, the device typically dissipates 140 mW. During standby, the entire part is powered down except the internal references ...
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... AD9273 600 EYE: ALL BITS 400 200 100 0 –100 –200 –400 –600 –1.5ns –1.0ns –0.5ns 0ns –200ps –100ps 0ps Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Less than 24 Inches on Standard FR-4 ULS: 2398/2398 ...
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... See Table 17 for details on enabling this feature. Two output clocks are provided to assist in capturing data from the AD9273. DCO± is used to clock the output data and is equal to six times the sampling clock rate. Data is clocked out of the AD9273 and must be captured on the rising and falling edges of the DCO± ...
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... Voltage Reference A stable and accurate 0.5 V voltage reference is built into the AD9273. This is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span of 2.0 V p-p for the ADC. VREF is set internally by default, but the VREF pin can be driven externally with a 1.0 V reference to achieve more accuracy ...
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... This ensures several tie points between the two during the reflow process. Using one continuous plane with no partitions only guarantees one tie point between the AD9273 and PCB. See Figure 68 for a PCB layout example. For more detailed infor- mation on packaging and for more PCB layout examples, see the AN-772 Application Note ...
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... In cases where multiple SDIO pins share a common connection, care should be taken to ensure that proper V Figure 69 shows the number of SDIO pins that can be connected together, assuming the same load as the AD9273, as well as the resulting V level ...
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... Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 70) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 70) Rev Page DON’T CARE AD9273 DON’T CARE ...
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... AD9273 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x04 to Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x2D) ...
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... Table 17. AD9273 Memory Map Register Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 Chip Configuration Registers 00 CHIP_PORT_CONFIG 0 LSB first off (default) 01 CHIP_ID 02 CHIP_GRADE X X Device Index and Transfer Registers 04 DEVICE_INDEX_2 DEVICE_INDEX_1 DEVICE_UPDATE X X ADC Functions Registers 08 Modes Clock ...
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... AD9273 Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 0F FLEX_CHANNEL_ Filter cutoff frequency control INPUT 0000 = 1.3 × 1/3 × f 0001 = 1.2 × 1/3 × f 0010 = 1.1 × 1/3 × f 0011 = 1.0 × 1/3 × f 0100 = 0.9 × 1/3 × f 0101 = 0.8 × 1/3 × f 0110 = 0.7 × 1/3 × f 1000 = 1.3 × 1/4.5 × f 1001 = 1.2 × 1/4.5 × f 1010 = 1.1 × ...
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... CWD3− (single ended) 11 1100 = CWD4− (single ended) 11 1101 = CWD5− (single ended) 11 1110 = CWD6− (single ended) 11 1111 = CWD7− (single ended) 0x xxxx = power down CW channel (default) Rev Page AD9273 Bit 0 Default Default Notes/ Bit 1 (LSB) Value ...
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... AD9273 OUTLINE DIMENSIONS 1.20 0.75 MAX 0.60 0.45 0° MIN 1.05 0.20 1.00 0.09 0.95 7° 3.5° 0.15 0° SEATING 0.05 0.08 MAX PLANE COPLANARITY VIEW A ROTATED 90 ° CCW BALL A1 INDICATOR TOP VIEW DETAIL A 1.40 MAX 16.00 BSC SQ 14.00 BSC SQ 76 100 PIN 1 TOP VIEW (PINS DOWN VIEW A COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD Figure 71. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] ...
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... AD9273BSVZ-25 −40°C to +85°C 1 AD9273BSVZRL-25 −40°C to +85°C 1 AD9273BBCZ-25 −40°C to +85°C 1 AD9273BBCZ-40 −40°C to +85°C 1 AD9273BBCZ-50 −40°C to +85°C 1 AD9273-50EBZ RoHS Compliant Part. Package Description 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] ...
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... AD9273 NOTES Rev Page ...
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... NOTES Rev Page AD9273 ...
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... AD9273 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07030-0-7/09(B) Rev Page ...