ADSP-2184 Analog Devices, ADSP-2184 Datasheet

ADSP-2184

Manufacturer Part Number

ADSP-2184

Description

DSP Microcomputer

Manufacturer

Analog Devices

Datasheet

1.ADSP-2184.pdf (31 pages)

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Download datasheet (214Kb)

ICE-Port is a trademark of Analog Devices, Inc.

All trademarks are the property of their respective holders.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

FEATURES

PERFORMANCE

25 ns Instruction Cycle Time 40 MIPS Sustained

Single-Cycle Instruction Execution

Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby

Low Power Dissipation in Idle Mode

INTEGRATION

ADSP-2100 Family Code Compatible, with Instruction

20K Bytes of On-Chip RAM, Configured as

Dual Purpose Program Memory for Both Instruction

Independent ALU, Multiplier/Accumulator and Barrel

Two Independent Data Address Generators

Powerful Program Sequencer Provides

Programmable 16-Bit Interval Timer with Prescaler

100-Lead LQFP

SYSTEM INTERFACE

16-Bit Internal DMA Port for High Speed Access to

4 MByte Byte Memory Interface for Storage of Data

8-Bit DMA to Byte Memory for Transparent Program

I/O Memory Interface with 2048 Locations Supports

Programmable Memory Strobe and Separate I/O Memory

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding

Automatic Booting of On-Chip Program Memory from

Performance

Every Instruction Cycle

Power Dissipation with 200 Cycle Recovery from

Power-Down Condition

Set Extensions

4K Words On-Chip Program Memory RAM and

4K Words On-Chip Data Memory RAM

and Data Storage

Shifter Computational Units

Zero Overhead Looping Conditional Instruction

Execution

On-Chip Memory (Mode Selectable)

Tables and Program Overlays (Made Selectable)

and Data Memory Transfers (Mode Selectable)

Parallel Peripherals (Mode Selectable)

Space Permits “Glueless” System Design

(Mode Selectable)

Hardware and Automatic Data Buffering

Byte-Wide External Memory, e.g., EPROM, or

Through Internal DMA Port

GENERAL DESCRIPTION

The ADSP-2184 is a single-chip microcomputer optimized for

digital signal processing (DSP) and other high speed numeric

processing applications.

The ADSP-2184 combines the ADSP-2100 family base archi-

tecture (three computational units, data address generators and

a program sequencer) with two serial ports, a 16-bit internal

DMA port, a byte DMA port, a programmable timer, Flag I/O,

extensive interrupt capabilities and on-chip program and data

memory.

The ADSP-2184 integrates 20K bytes of on-chip memory con-

figured as 4K words (24-bit) of program RAM and 4K words

(16-bit) of data RAM. Power-down circuitry is also provided to

meet the low power needs of battery operated portable equip-

ment. The ADSP-2184 is available in 100-lead LQFP package.

In addition, the ADSP-2184 supports instructions that include

bit manipulations—bit set, bit clear, bit toggle, bit test— ALU

constants, multiplication instruction (x squared), biased round-

ing, result free ALU operations, I/O memory transfers, and

global interrupt masking for increased flexibility.

Fabricated in a high speed, double metal, low power, CMOS

process, the ADSP-2184 operates with a 25 ns instruction cycle

time. Every instruction can execute in a single processor cycle.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

DATA ADDRESS

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System

UART Emulation through Software SPORT Reconfiguration

ICE-Port™ Emulator Interface Supports Debugging

GENERATORS

DAG 1

ALU

Signaling

in Final Systems

ARITHMETIC UNITS

ADSP-2100 BASE

ARCHITECTURE

DAG 2

MAC

SHIFTER

SEQUENCER

FUNCTIONAL BLOCK DIAGRAM

PROGRAM

PROGRAM MEMORY DATA

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

DATA MEMORY DATA

World Wide Web Site: http://www.analog.com

DSP Microcomputer

PROGRAM

MEMORY

SPORT 0

SERIAL PORTS

POWER-DOWN

MEMORY

CONTROL

SPORT 1

MEMORY

DATA

ADSP-2184

PROGRAMMABLE

TIMER

FLAGS

AND

I/O

FULL MEMORY

CONTROLLER

HOST MODE

EXTERNAL

INTERNAL

ADDRESS

BYTE DMA

DATA

PORT

DMA

BUS

MODE

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