am79c961 Advanced Micro Devices, am79c961 Datasheet

am79c961

Manufacturer Part Number

am79c961

Description

Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa

Manufacturer

Advanced Micro Devices

Datasheet

1.AM79C961.pdf (173 pages)

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Am79C961

PCnet

for ISA

DISTINCTIVE CHARACTERISTICS

GENERAL DESCRIPTION

The PCnet-ISA

troller, is a highly integrated system solution for the

PC-AT Industry Standard Architecture (ISA ) architec-

ture. It is designed to provide flexibility and compatibility

with any existing PC application. This highly integrated

132-pin VLSI device is specifically designed to reduce

parts count and cost, and addresses applications where

higher system throughput is desired. The PCnet-ISA

Publication# 18183

Issue Date: April 1994

Single-chip Ethernet controller for the Industry

Standard Architecture (ISA) and Extended

Industry Standard Architecture (EISA) buses

Supports IEEE 802.3/ANSI 8802-3 and Ethernet

standards

Direct interface to the ISA or EISA bus

Software compatible with AMD’s Am7990

LANCE register and descriptor architecture

Low power, CMOS design with sleep mode

allows reduced power consumption for critical

battery powered applications

Individual 136-byte transmit and 128-byte

receive FIFOs provide packet buffering for

increased system latency, and support the

following features:

— Automatic retransmission with no FIFO

— Automatic receive stripping and transmit

— Automatic runt packet rejection

— Automatic deletion of received collision

Dynamic transmit FCS generation program-

mable on a frame-by-frame basis

Single +5 V power supply

Internal/external loopback capabilities

Supports 8K, 16K, 32K, and 64K Boot PROMs

or Flash for diskless node applications

Supports Microsoft’s Plug and Play System

configuration for jumperless designs

Supports staggered AT bus drive for reduced

noise and ground bounce

Supports 8 interrupts on chip

reload

padding (individually programmable)

frames

PRELIMINARY

-ISA

Rev. B

controller, a single-chip Ethernet con-

Jumperless Single-Chip Ethernet Controller

Amendment /0

This document contains information on a product under development at Advanced Micro Devices, Inc.

The information is intended to help you to evaluate this product. AMD reserves the right to change or

discontinue work on this proposed product without notice.

controller is fabricated with AMD’s advanced low-power

CMOS process to provide low standby current for power

sensitive applications.

The PCnet-ISA

dual architecture that can be configured in two different

operating modes to suit a particular PC application. In

the Bus Master Mode all transfers are performed using

Look Ahead Packet Processing (LAPP) allows

protocol analysis to begin before end of

receive frame

Supports 4 DMA channels on chip

Supports 16 I/O locations

Supports 16 boot PROM locations

Provides integrated Attachment Unit Interface

(AUI) and 10BASE-T transceiver with 2 modes

of port selection:

— Automatic selection of AUI or 10BASE-T

— Software selection of AUI or 10BASE-T

Automatic Twisted Pair receive polarity

detection and automatic correction of the

receive polarity

Supports bus-master and shared-memory

architectures to fit in any PC application

Supports edge and level-sensitive interrupts

DMA Buffer Management Unit for reduced CPU

intervention which allows higher throughput by

by-passing the platform DMA

JTAG Boundary Scan (IEEE 1149.1) test access

port interface for board level production test

Integrated Manchester Encoder/Decoder

Supports the following types of network

interfaces:

— AUI to external 10BASE2, 10BASE5,

— Internal 10BASE-T transceiver with Smart

Supports LANCE General Purpose Serial

Interface (GPSI)

132-pin PQFP package

10BASE-T or 10BASE-F MAU

Squelch to Twisted Pair medium

controller is a DMA-based device with a

Advanced

Devices

Micro

1-475

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