DS1374 Maxim, DS1374 Datasheet
DS1374
Available stocks
Related parts for DS1374
DS1374 Summary of contents
Page 1
... C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output General Description The DS1374 is a 32-bit binary counter designed to contin- uously count time in seconds. An additional counter gen- erates a periodic alarm or serves as a watchdog timer. If disabled, this counter can be used as 3 bytes of non- volatile (NV) RAM ...
Page 2
... Storage Temperature Range .............................-55°C to +125°C Lead Temperature (soldering, 10s) .................................+260°C Soldering Temperature (reflow) .......................................+260°C CONDITIONS DS1374-33 V DS1374-3 CC DS1374-18 V (Note (Note (Note 3) PU DS1374-33 V DS1374-3 PF DS1374-18 DS1374-33 DS1374-3, DS1374-18 ) (Note 1) JC MIN TYP MAX UNITS 2.97 3.3 5.50 2.7 3.0 3.3 V 1.71 1.8 1. ...
Page 3
... LORST OLSDA V > 1.71V < V < 2V 0.2 V OL1 CC OL 1.3V < V < 1.71V 0 DS1374-18 I DS1374-3 CCA DS1374-33 DS1374-18 I DS1374-3 CCS DS1374-33 CONDITIONS (Note 15) (Notes 15, 16) _____________________________________________________________________ MIN TYP MAX 250 2000 4000 - -200 +1 3.0 3.0 3.0 CC 250 CC 75 150 ...
Page 4
I C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output AC ELECTRICAL CHARACTERISTICS ( -40°C to +85°C, unless otherwise noted.) (Note 2) (Figure 1) CC CC(MIN) CC(MAX) A PARAMETER ...
Page 5
... B Note 18: After this period, the first clock pulse is generated. Note 19: The maximum t only has to be met if the device does not stretch the low period (t HD:DAT Note 20: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V nal) to bridge the undefined region of the falling edge of SCL ...
Page 6
I C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output SDA t BUF t LOW SCL t HD:STA STOP START 2 Figure 1. Data Transfer Serial Bus RST PB DB Figure 2. Pushbutton ...
Page 7
I C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output (V = +3.3V +25°C, unless otherwise noted vs. V BAT0SC1 BAT SQUARE-WAVE OFF 550 500 450 400 ...
Page 8
... Supply voltage must be held between 1.3V and 3.7V (-18 and - delay. RST 1Hz 4.096kHz 8.192kHz MUX 32.768kHz 32-BIT COUNTER ALARM/ COUNTER WATCHDOG STAT/CTRL/ TRICKLE DS1374 Pin Description ) of 6pF. Pin X1 is the input to the L SQW 1Hz/4.096kHz INT INT CONTROL 24-BIT RST RST CONTROL ...
Page 9
... X2 CRYSTAL Figure 5. Oscillator Circuit Showing Internal Bias Network Detailed Description The DS1374 is a real-time clock with an I face. It provides elapsed seconds from a user-defined starting point in a 32-bit counter (Figure 4). A 24-bit counter can be configured as either a watchdog counter or an alarm counter. An on-chip oscillator cir- cuit uses a customer-supplied 32 ...
Page 10
... Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. 10 ____________________________________________________________________ Table 3 shows the address map for the DS1374 regis- ters. During a multibyte access, the address pointer level. The wraps around to location 00h when it reaches the end of CC the register space (08h) ...
Page 11
... After the internal 250ms timer has expired, the device continues to monitor the RST line. If the line is still low, the DS1374 continues to moni- tor the line, looking for a rising edge. Upon detecting release, the DS1374 forces the RST pin low and holds it low for an additional 250ms ...
Page 12
... When this bit is set to logic 1, the oscilla- tor is stopped and the DS1374 is placed into a low-power standby mode (I ). This bit is clear (logic DDR 0) when power is first applied. When the DS1374 is powered the oscillator is always on regardless CC of the state of the EOSC bit. ...
Page 13
... If WD/ALM is set to 1 and the AIE bit = 1, the INT pin pulses low for 250ms when the WD/ALM counter reaches zero and sets the pulse completion, the DS1374 clears the AF bit to zero. If the 250ms pulse is active, writing AF to zero does not truncate the pulse. ...
Page 14
... ACK and SCL. A standard mode (100kHz max clock rate) and a fast mode (400kHz max clock rate) are defined within the bus specifications. The DS1374 works in both modes. The following bus protocol has been defined (Figure 8): • Data transfer can be initiated only when the bus is not busy. • ...
Page 15
... START condition. Since a repeated START condi- tion is also the beginning of the next serial transfer, the bus is not released. The DS1374 can operate in the following two modes: Slave Receiver Mode (Write Mode): Serial data and clock data are received through SDA and SCL. ...
Page 16
... Trickle Charger and Reset Input/Output After the DS1374 acknowledges the slave address + write bit, the master transmits a register address to the DS1374. This sets the register pointer on the DS1374, with the DS1374 acknowledging the trans- fer. The master can then transmit zero or more bytes of data, with the DS1374 acknowledging each byte received ...
Page 17
... RoHS status. PACKAGE TYPE 16 SO (0.300”) 10 µSOP (3.0mm) ____________________________________________________________________ Pin Configurations 1 16 SDA 2 15 GND 3 14 RST BACKUP DS1374C N.C. N. (0.300") Package Information PACKAGE OUTLINE LAND CODE NO. PATTERN NO. ...
Page 18
... Package Information table Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...