hi-8482 Holt Integrated Circuits, Inc., hi-8482 Datasheet
hi-8482
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hi-8482 Summary of contents
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... March 2007 GENERAL DESCRIPTION The HI-8482 bus interface unit is a silicon gate CMOS de- vice designed as a dual differential line receiver in accor- dance with the requirements of the ARINC 429 bus speci- fication. The device translates incoming ARINC 429 sig- nals to normal CMOS/TTL levels on each of its two inde- pendent receive channels ...
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... STATE ONE NULL ZERO The HI-8482 guarantees recognition of these levels with a common mode voltage with respect to GND less than ±5V for the worst case condition. NOISE The input hysteresis is set to reject voltage level transi- tions in the undefined region between the maximum ...
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... HI-8482 ground (GND) connection should be sturdy and isolated from large switching currents to provide a quiet ground reference. The HI-8482 can be used with HI-3182 or HI-8585 Line Drivers to provide a complete analog ARINC 429 interface solution. A simple application, which can be used in systems requiring a repeater type circuit for long transmissions or for test interfaces, is given in The Figure 3 ...
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... INPUT ARINC input terminal A of channel 2 TIMING DIAGRAMS +10V ARINC DIFFERENTIAL 0V INPUT -10V OUTA OUTB +5V TESTA 0V +5V TESTB 0V OUTA (test) OUTB (test) HI-8482 SYMBOL FUNCTION IN2B INPUT OUT1A OUTPUT OUT1B OUTPUT OUT2A OUTPUT OUT2B OUTPUT TESTA INPUT TESTB INPUT +V POWER L +Vs ...
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... Notes: 1. Guaranteed by design. HI-8482 Voltage at ARINC Inputs: .......................................................-29V to +29V Voltage at Any Other Input:.............................................-0. 0.3V Output Short Circuit Protected: .............................................Not Protected Storage Temperature Range: .........................................-65°C to +150°C Soldering Temperature: (Ceramic).................................30 sec. at +300°C SYMBOL TEST CONDITIONS ...
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... ADDITIONAL HI-8482 PIN CONFIGURATIONS (All 20-Pin Package Configurations) IN2B - 4 HI-8482U OUT2B - 5 HI-8482UT IN2A - 6 20-PIN CAP2A - 7 J-LEAD OUT2A - 8 CERQUAD - TESTA - 2 CAP2B - 3 HI-8482C HI-8482CT IN2B - 4 HI-8482CM-01 OUT2B - 5 IN2A - 6 20-PIN CERAMIC CAP2A - 7 SIDE-BRAZED OUT2A - 8 DIP + N HI-8482 18 - IN1A IN2B - CAP1B OUT2B - 5 ...
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... PLCC & Wide Body SOIC) PART NUMBER Blank F PART NUMBER Blank I T PART NUMBER J PS HI-8482 TEMPERATURE BURN FLOW RANGE -40°C TO +85°C I -55°C TO +125°C T -55°C TO +125°C M PACKAGE DESCRIPTION 20 PIN CERAMIC SIDE BRAZED DIP (20C) 20 PIN CERAMIC LEADLESS CHIP CARRIER (20S) ...
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... BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8482 PACKAGE DIMENSIONS .5035 ± .0075 (12.789 ± .191) .295 ± .002 (7.493 ± .051) .018 typ (.457) 0° to 8° ...
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... BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8482 PACKAGE DIMENSIONS .070 max 1.060 max (1.778 max) (26.924 max) .288 ±.005 (7.315 ±.127) ...
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... J-LEAD CERQUAD .375 ± .008 (9.525 ± .203) .040 typ (1.016) .019 ± .003 (.483 ±.076) HI-8482 PACKAGE DIMENSIONS .080 ±.020 3 PLCS (2.032 ±.508) .075 ±.004 (1.905 ±.101) .009R .006 (.229R ±.152) .050 (1 ...