ICS2008 Integrated Circuit System, ICS2008 Datasheet

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ICS2008

Manufacturer Part Number
ICS2008
Description
Smptetime Code Receiver / Generator
Manufacturer
Integrated Circuit System
Datasheet

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Block Diagram
General Description
The ICS2008B, SMPTE Time Code Receiver / Generator
chip, is a VLSI device designed in a low power CMOS
process. This device provides the timing coordination for
Multimedia sight and sound events. Although it is aimed at
a PC Multimedia environment, the ICS2008B is easily
integrated into products requiring SMPTE time code
generation and/or reception in LTC (Longitudinal Time
Code) and/or VITC (Vertical Interval Time Code) formats
and MTC (MIDI Time Code) translation.
Taking its input from composite video, S-Video, or an
audio track, the ICS2008B can read SMPTE time code in
VITC and LTC formats. Time code output formats are LTC
and VITC. All are available simultaneously. A UART is
provided for the user to support MTC or tape transport
control.
The processor interface is compatible with the IBM PC and
ISA bus compatible computers and is easily interfaced to
other processors.
The ICS2008B is an improved version of the ICS2008,
with additional features and capabilities.
ICS2008 ICS2008B 2008 2008B
SMPTE Time Code Receiver/Generator
ICS2008B Rev B 6/6/01
Integrated
Circuit
Systems, Inc.
Features
• Internal and external sync sources
• LTC and VITC Generators
• LTC Receiver
• VITC Receiver
New, Improved Features
• Time Code Burn-in Window with programmable
• Internal Timer, allows 1/4 Frame MIDI Time Code
• LTC edge rate control, conforms to EBU Tr and Tf
• Improved video timing lock during VCR pause and
• VITC search mode, will search through VBI lines until
• New UART frequency of 38.4 K baud for tape transport
• Improved video output performance
– Genlock to video or house sync inputs
– Internally generated timing from oscillator input
– External click input
– Real Time SMPTE Rates: 30 Hz, 29.97 Hz,
– Time Code Modes: Drop Frame and Color Frame
– VITC can be inserted on two lines from 10-40
– Jam Sync, freewheeling, error bypass/correction,
– Meets SMPTE and EBU LTC specifications
– Synchronize bit rates from 1/30
– Reads code from any or all selected scan lines.
– Meets SMPTE VITC specifications
position, size and character attributes
Messages
specification
shuttle modes
VITC is found
control
25 Hz, 24 Hz
(SMPTE specifies lines 10-20)
and plus-one-frame capability
nominal playback speed.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
th
ICS2008B
nominal to 80X

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ICS2008 Summary of contents

Page 1

... Code) and/or VITC (Vertical Interval Time Code) formats and MTC (MIDI Time Code) translation. Taking its input from composite video, S-Video audio track, the ICS2008B can read SMPTE time code in VITC and LTC formats. Time code output formats are LTC and VITC. All are available simultaneously. A UART is provided for the user to support MTC or tape transport control ...

Page 2

... ICS2008B Package Pinouts LTCOUT 7 LFC 8 XTAL2 9 XTAL1 10 AVDD 11 12 AVSS COUT 13 YOUT ICS2008B Rev B 6/6/ IOW * 35 VDD 34 VSS 33 IOR* 32 UARTCS PTECS ...

Page 3

... Read Enable (active low) I Write Enable (active low) I SMPTE port chip select (active low) I UART chip select (active low) I Master reset (active high) I/O Bi-directional data bus O Interrupt Request (active high) P Analog Analog Ground P Digital Digital 2008 2008B ICS2008 3 ICS2008B DESCRIPTION ICS2008B Rev B 6/6/01 ...

Page 4

... ICS2008B chip. It also describes how those registers can be utilized by the software to facilitate specific application services. Hardware Environments The ICS2008B operates as a peripheral to a processor such single chip microprocessor. Many of the real time requirements are satisfied by double buffering both incoming and outgoing time codes. ...

Page 5

... MIDI time code messages. Processor Interface The ICS2008B supports standard microprocessor interfaces and busses, such as the PC bus, to allow access to six control/ status and data registers. These six registers are organized into two groups, one set of four for SMPTE control and the other set of two for direct UART port control ...

Page 6

... VLOCK — This is a hardware driven bit which indicates that genlock has been achieved with the selected video SYNC source. ICS2008B Rev B 6/6/01 FRAME & FIELD — The hardware SYNC separator detects the field and frame from the selected video input. The even/ odd fields are identified by a 1/0 in bit 6 ...

Page 7

... VITC Write Enable – Enables the output of VITC code on the specified line. 7 ICS2008B – (Frame) – (Seconds) – (Minutes) – (Hours " ICS2008B Rev B 6/6/01 ...

Page 8

... NOCODE — This bit is set when a framing error occurs in the VITC code, i.e. not all the bits of the code were received by the time the end of the video line occurred. Both CRCERR and NOCODE must be zero to qualify a VITC code. ICS2008B Rev B 6/6/01 Video Control Register IR32 IR32 ...

Page 9

... C: 0dB 1: 5: -21dB 3dB 2: 6: -18dB 6dB 3: 7: -15dB 9dB Reserved DIVIDER VALUE 30 Hz BA6h BA9h 25 Hz DFBh 24 Hz E90h LTC Bit Time (write only) IR36 – (low byte) IR37 – (high byte) ICS2008B Rev B 6/6/01 ...

Page 10

... The 100 kHz input is actually 100.126 kHz the crystal frequency divided by 143. RUN — This bit starts and stops the timer. When set to one, the timer is running. When set to zero, the timer is stopped. ICS2008B Rev B 6/6/ IR3E Burn-in Window Attributes ...

Page 11

... VITC WRITE LINE VITC WRITE LINE VITC READ LINE VITC READ LINE VSYNCSEL VTRES 0 LTXFREE EDGE RATE 0 0 TIMER VALUE (high) WINDOW ATTRIBUTE ICS2008B Rev B 6/6/01 0 GEN_EN BLINK ...

Page 12

... RIE — Bit 7, Receive interrupt enable, when set to one, enables the UART to interrupt the processor when the receive buffer is full or a receive overrun has occurred. ICS2008B Rev B 6/6/ RBF — Bit 0, Receive Buffer Full, is set to 1 when read data is available in the UART data register ...

Page 13

... LTC Output Voltage Amplitude Range Analog VDD Supply Current Digital VDD Supply Current + 0 SYMBOL MIN TYP VIL 0.5 VIH 2.0 IIL CIN VOL VOH 2.4 IOZ 1.0 0.1 0.3 VDD/3 1.0 2 IDD1 IDD2 13 ICS2008B MAX UNITS 0.8 V VDD+0 0 Vp-p Vp-p VDD+0 Vp-p Vp ICS2008B Rev B 6/6/01 ...

Page 14

... Register [1:0] = 00) UART Port Bit Rate (Command Register [1:0] = 01) UART Port Bit Rate (Command Register [1:0] = 10) Notes: 1. This timing parameter must be met for proper operation of indirect register access using auto-increment. FIGURE 3 — Host Processor Bus Timing ICS2008B Rev B 6/6/01 SYMBOL MIN TYP t 20 ACS t ...

Page 15

... LTCIN – should be capacitively coupled to the ground reference of that source. If the LTC source is digital, set the LTCIN – to the desired threshold, and connect the digital source to LTCIN+. 15 ICS2008B Fig Video Output Fig Self Biased Inputs ICS2008B Rev B 6/6/01 ...

Page 16

... This makes the ICS2008B flexible enough for a broad range of ap- plications without making the processing requirements on the host system too great. ...

Page 17

... VITC receive and generate operations to be com- plete before processing VITC. The VLOCK bit in the SMPTE1 register indicates whether the ICS2008B is genlocked to the selected video source. Without the VLOCK status set to one, no VITC read will occur. When VLOCK is set to one and the control registers are prop- erly initialized, VITC data are received a byte at a time from the video signal and written to the VITC Read registers ...

Page 18

... Example: ICS 2008B X Package Type V = PLCC; Y- TQFP Evaluation Board Device Type Prefix ICS2008B Rev B 6/6/01 PLCC 44-PIN PACKAGE ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to 18 obtain the latest version of all device data to verify that any ...

Page 19

... ICS2008B ICS2008B Rev B 6/6/01 ...

Page 20

... ICS2008B Document Revision History Rev A (First Release) Started with ICS2008A Rev D Source Document General cleanup for readability. Rev B Correct C2 pin number in Pin Description (pg 3) Call out tieing LFC pin high in Pin Description (pg 3) Added Document Revision History. (pg 20) Added Corporate Contact Information (pg 21) ...

Page 21

... Integrated Circuit Systems, Inc. Corporate Headquarters: 2435 Boulevard of the Generals P.O. Box 968 Valley Forge, PA 19482-0968 Telephone: Fax: San Jose Operations: 525 Race Street San Jose, CA 95126-3448 Telephone: Fax: Web Site: http://www.icst.com 610-630-5300 610-630-5399 408-297-1201 408-925-9460 21 ICS2008B ICS2008B Rev B 6/6/01 ...

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